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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-07-10 19:53:57 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-07-10 19:53:57 +0000 |
| commit | 6c29c5acfe17260c1b3b30663636d34033bdde53 (patch) | |
| tree | fac262cfbdaccb245cd7c968a14d549a29fef3b6 /llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll | |
| parent | fda531820484369b48e657abbbeaa969d4a94002 (diff) | |
| download | bcm5719-llvm-6c29c5acfe17260c1b3b30663636d34033bdde53.tar.gz bcm5719-llvm-6c29c5acfe17260c1b3b30663636d34033bdde53.zip | |
AMDGPU: Allow SIShrinkInstructions to work in non-SSA
Immediates can be folded as long as the immediate is a vreg.
Also undo commuting instructions if it didn't fold an immediate.
llvm-svn: 307575
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll b/llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll index 8c74ec683d9..0f09fa17423 100644 --- a/llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll +++ b/llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll @@ -6,7 +6,7 @@ ; GCN: buffer_load_dword [[VAL:v[0-9]+]], ; GCN: v_lshrrev_b32_e32 [[SHR:v[0-9]+]], 16, [[VAL]] ; GCN: v_lshlrev_b32_e32 [[SHL:v[0-9]+]], 16, [[SHR]] -; GCN: v_or_b32_e32 v[[OR:[0-9]+]], [[SHL]], [[SHR]] +; GCN: v_or_b32_e32 v[[OR:[0-9]+]], [[SHR]], [[SHL]] ; GCN: v_mov_b32_e32 v[[COPY:[0-9]+]], v[[OR]] ; GCN: buffer_store_dwordx2 v{{\[}}[[OR]]:[[COPY]]{{\]}} define amdgpu_kernel void @scalar_to_vector_v2i32(<4 x i16> addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { |
