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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-11-16 20:35:23 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-11-16 20:35:23 +0000 |
| commit | 3b36bb1d8780caeb122ee86cf2f44e397cb028ea (patch) | |
| tree | 8bfac477c9af17ec001ff7b7f479d6cd7dd5e91f /llvm/test/CodeGen/AMDGPU/sad.ll | |
| parent | 1b9560ffd61f3f4c2089c4971ebce0cfb4932adf (diff) | |
| download | bcm5719-llvm-3b36bb1d8780caeb122ee86cf2f44e397cb028ea.tar.gz bcm5719-llvm-3b36bb1d8780caeb122ee86cf2f44e397cb028ea.zip | |
AMDGPU: Enable ConstrainCopy DAG mutation
This fixes a probably unintended divergence from the default
scheduler behavior.
llvm-svn: 287146
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/sad.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/sad.ll | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/sad.ll b/llvm/test/CodeGen/AMDGPU/sad.ll index 53448340163..846825a189b 100644 --- a/llvm/test/CodeGen/AMDGPU/sad.ll +++ b/llvm/test/CodeGen/AMDGPU/sad.ll @@ -134,8 +134,8 @@ define void @v_sad_u32_multi_use_sub_pat2(i32 addrspace(1)* %out, i32 %a, i32 %b ; GCN-LABEL: {{^}}v_sad_u32_multi_use_select_pat2: ; GCN: s_sub_i32 s{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}} -; GCN: v_cmp_gt_u32_e32 vcc, s{{[0-9]+}}, v{{[0-9]+}} -; GCN: s_sub_i32 s{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}} +; GCN-DAG: s_sub_i32 s{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}} +; GCN-DAG: v_cmp_gt_u32_e32 vcc, s{{[0-9]+}}, v{{[0-9]+}} define void @v_sad_u32_multi_use_select_pat2(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) { %icmp0 = icmp ugt i32 %a, %b %sub0 = sub i32 %a, %b |
