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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-07-15 21:27:08 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-07-15 21:27:08 +0000 |
| commit | 82e5e1e564d77dcd8babbfa9c2850912f94786e4 (patch) | |
| tree | 81e53dcf93d1effa226d94c94967d4646f2cbcaa /llvm/test/CodeGen/AMDGPU/pv.ll | |
| parent | 11d3e21f2b7297ddcb213f6892134b5c8f2a520b (diff) | |
| download | bcm5719-llvm-82e5e1e564d77dcd8babbfa9c2850912f94786e4.tar.gz bcm5719-llvm-82e5e1e564d77dcd8babbfa9c2850912f94786e4.zip | |
AMDGPU: Fix TargetPrefix for remaining r600 intrinsics
llvm-svn: 275619
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/pv.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/pv.ll | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/pv.ll b/llvm/test/CodeGen/AMDGPU/pv.ll index 953833bd998..d5f9833d6ad 100644 --- a/llvm/test/CodeGen/AMDGPU/pv.ll +++ b/llvm/test/CodeGen/AMDGPU/pv.ll @@ -209,12 +209,12 @@ main_body: %201 = insertelement <4 x float> %200, float %79, i32 1 %202 = insertelement <4 x float> %201, float %83, i32 2 %203 = insertelement <4 x float> %202, float %87, i32 3 - call void @llvm.R600.store.swizzle(<4 x float> %203, i32 60, i32 1) + call void @llvm.r600.store.swizzle(<4 x float> %203, i32 60, i32 1) %204 = insertelement <4 x float> undef, float %197, i32 0 %205 = insertelement <4 x float> %204, float %198, i32 1 %206 = insertelement <4 x float> %205, float %199, i32 2 %207 = insertelement <4 x float> %206, float %117, i32 3 - call void @llvm.R600.store.swizzle(<4 x float> %207, i32 0, i32 2) + call void @llvm.r600.store.swizzle(<4 x float> %207, i32 0, i32 2) ret void } @@ -233,7 +233,7 @@ declare float @llvm.AMDGPU.clamp.f32(float, float, float) #1 ; Function Attrs: nounwind readonly declare float @llvm.pow.f32(float, float) #2 -declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) #3 +declare void @llvm.r600.store.swizzle(<4 x float>, i32, i32) #3 attributes #1 = { nounwind readnone } attributes #2 = { nounwind readonly } |
