diff options
| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-09-09 23:32:53 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-09-09 23:32:53 +0000 |
| commit | 124384f08d4cb9b8c698951ed67fd6db79a15d15 (patch) | |
| tree | bef6b9dcd6420bcf678b0e617646e70bb06947c8 /llvm/test/CodeGen/AMDGPU/or.ll | |
| parent | 8dc0e0943b9e9b864b91a50e991392db09f2dc49 (diff) | |
| download | bcm5719-llvm-124384f08d4cb9b8c698951ed67fd6db79a15d15.tar.gz bcm5719-llvm-124384f08d4cb9b8c698951ed67fd6db79a15d15.zip | |
AMDGPU: Fix immediate folding logic when shrinking instructions
If the literal is being folded into src0, it doesn't matter
if it's an SGPR because it's being replaced with the literal.
Also fixes initially selecting 32-bit versions of some instructions
which also confused commuting.
llvm-svn: 281117
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/or.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/or.ll | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/or.ll b/llvm/test/CodeGen/AMDGPU/or.ll index 9b90ff798ca..56f54cf7c5e 100644 --- a/llvm/test/CodeGen/AMDGPU/or.ll +++ b/llvm/test/CodeGen/AMDGPU/or.ll @@ -113,11 +113,9 @@ define void @scalar_vector_or_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %a, } ; FUNC-LABEL: {{^}}vector_or_i64_loadimm: -; SI-DAG: s_mov_b32 [[LO_S_IMM:s[0-9]+]], 0xdf77987f -; SI-DAG: s_movk_i32 [[HI_S_IMM:s[0-9]+]], 0x146f ; SI-DAG: buffer_load_dwordx2 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, -; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[LO_S_IMM]], v[[LO_VREG]] -; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[HI_S_IMM]], v[[HI_VREG]] +; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, 0xdf77987f, v[[LO_VREG]] +; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, 0x146f, v[[HI_VREG]] ; SI: s_endpgm define void @vector_or_i64_loadimm(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) { %loada = load i64, i64 addrspace(1)* %a, align 8 |
