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| author | Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> | 2017-09-19 20:54:38 +0000 |
|---|---|---|
| committer | Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> | 2017-09-19 20:54:38 +0000 |
| commit | d4ae470d2e7a967331a5bb3ae5be29a4f0b6c764 (patch) | |
| tree | 9065b407288d50bfeb20d5827ea6fb2dcbf008ca /llvm/test/CodeGen/AMDGPU/move-addr64-rsrc-dead-subreg-writes.ll | |
| parent | 59a01a958a55c75af4076e35ba67e2a4a38d8dce (diff) | |
| download | bcm5719-llvm-d4ae470d2e7a967331a5bb3ae5be29a4f0b6c764.tar.gz bcm5719-llvm-d4ae470d2e7a967331a5bb3ae5be29a4f0b6c764.zip | |
[AMDGPU] Prevent post-RA scheduler from breaking memory clauses
The pre-RA scheduler does load/store clustering, but post-RA
scheduler undoes it. Add mutation to prevent it.
Differential Revision: https://reviews.llvm.org/D38014
llvm-svn: 313670
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/move-addr64-rsrc-dead-subreg-writes.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/move-addr64-rsrc-dead-subreg-writes.ll | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/move-addr64-rsrc-dead-subreg-writes.ll b/llvm/test/CodeGen/AMDGPU/move-addr64-rsrc-dead-subreg-writes.ll index e1fb00a1de3..5bc59c9f636 100644 --- a/llvm/test/CodeGen/AMDGPU/move-addr64-rsrc-dead-subreg-writes.ll +++ b/llvm/test/CodeGen/AMDGPU/move-addr64-rsrc-dead-subreg-writes.ll @@ -6,11 +6,11 @@ ; FIXME: We should be able to use the SGPR directly as src0 to v_add_i32 ; GCN-LABEL: {{^}}clobber_vgpr_pair_pointer_add: -; GCN-DAG: s_load_dwordx2 s{{\[}}[[ARG1LO:[0-9]+]]:[[ARG1HI:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x0{{$}} -; GCN-DAG: buffer_load_dwordx2 v{{\[}}[[LDPTRLO:[0-9]+]]:[[LDPTRHI:[0-9]+]]{{\]}} +; GCN: s_load_dwordx2 s{{\[}}[[ARG1LO:[0-9]+]]:[[ARG1HI:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x0{{$}} ; GCN-NOT: v_mov_b32 ; GCN: v_mov_b32_e32 v[[VARG1LO:[0-9]+]], s[[ARG1LO]] +; GCN: buffer_load_dwordx2 v{{\[}}[[LDPTRLO:[0-9]+]]:[[LDPTRHI:[0-9]+]]{{\]}} ; GCN-NOT: v_mov_b32 ; GCN: v_mov_b32_e32 v[[VARG1HI:[0-9]+]], s[[ARG1HI]] ; GCN-NOT: v_mov_b32 |
