diff options
| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-01-29 10:05:16 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-01-29 10:05:16 +0000 |
| commit | 295875efda08d539d536528d3286a64bbaee56e0 (patch) | |
| tree | f185c662752f54654ab8c29d6f32dd1cc025fc3b /llvm/test/CodeGen/AMDGPU/mad_int24.ll | |
| parent | 5d095c91ee10b1ad7b68b67c6c2e520d1cc61637 (diff) | |
| download | bcm5719-llvm-295875efda08d539d536528d3286a64bbaee56e0.tar.gz bcm5719-llvm-295875efda08d539d536528d3286a64bbaee56e0.zip | |
AMDGPU: Remove 24-bit intrinsics
The known bit matching code seems to work reasonably well,
so these shouldn't really be needed.
llvm-svn: 259180
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/mad_int24.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/mad_int24.ll | 11 |
1 files changed, 0 insertions, 11 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/mad_int24.ll b/llvm/test/CodeGen/AMDGPU/mad_int24.ll index 86d75a63ca4..def14c10d42 100644 --- a/llvm/test/CodeGen/AMDGPU/mad_int24.ll +++ b/llvm/test/CodeGen/AMDGPU/mad_int24.ll @@ -3,8 +3,6 @@ ; RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI --check-prefix=FUNC ; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s --check-prefix=SI --check-prefix=FUNC -declare i32 @llvm.AMDGPU.imul24(i32, i32) nounwind readnone - ; FUNC-LABEL: {{^}}i32_mad24: ; Signed 24-bit multiply is not supported on pre-Cayman GPUs. ; EG: MULLO_INT @@ -24,12 +22,3 @@ entry: store i32 %3, i32 addrspace(1)* %out ret void } - -; FUNC-LABEL: @test_imul24 -; SI: v_mad_i32_i24 -define void @test_imul24(i32 addrspace(1)* %out, i32 %src0, i32 %src1, i32 %src2) nounwind { - %mul = call i32 @llvm.AMDGPU.imul24(i32 %src0, i32 %src1) nounwind readnone - %add = add i32 %mul, %src2 - store i32 %add, i32 addrspace(1)* %out, align 4 - ret void -} |
