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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-11-29 00:55:57 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-11-29 00:55:57 +0000 |
| commit | 3f71c0e3ee5be2cf0b1d9e37e8e1ade5bb7bdbe6 (patch) | |
| tree | d4cf261c267dc8e08f62918193770b07d6b81be3 /llvm/test/CodeGen/AMDGPU/load-local-i64.ll | |
| parent | ba874ad83ed7c482e5da51385a6df0647f3b5c1a (diff) | |
| download | bcm5719-llvm-3f71c0e3ee5be2cf0b1d9e37e8e1ade5bb7bdbe6.tar.gz bcm5719-llvm-3f71c0e3ee5be2cf0b1d9e37e8e1ade5bb7bdbe6.zip | |
AMDGPU: Select DS insts without m0 initialization
GFX9 stopped using m0 for most DS instructions. Select
a different instruction without the use. I think this will
be less error prone than trying to manually maintain m0
uses as needed.
llvm-svn: 319270
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/load-local-i64.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/load-local-i64.ll | 27 |
1 files changed, 23 insertions, 4 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/load-local-i64.ll b/llvm/test/CodeGen/AMDGPU/load-local-i64.ll index 0c719a9e0bf..376f6f513c3 100644 --- a/llvm/test/CodeGen/AMDGPU/load-local-i64.ll +++ b/llvm/test/CodeGen/AMDGPU/load-local-i64.ll @@ -1,9 +1,13 @@ -; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s -; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s -; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s -; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SICIVI,FUNC %s +; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SICIVI,FUNC %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SICIVI,FUNC %s +; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9,FUNC %s +; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefixes=EG,FUNC %s ; FUNC-LABEL: {{^}}local_load_i64: +; SICIVI: s_mov_b32 m0 +; GFX9-NOT: m0 + ; GCN: ds_read_b64 [[VAL:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}}{{$}} ; GCN: ds_write_b64 v{{[0-9]+}}, [[VAL]] @@ -16,6 +20,9 @@ define amdgpu_kernel void @local_load_i64(i64 addrspace(3)* %out, i64 addrspace( } ; FUNC-LABEL: {{^}}local_load_v2i64: +; SICIVI: s_mov_b32 m0 +; GFX9-NOT: m0 + ; GCN: ds_read2_b64 ; EG: LDS_READ_RET @@ -30,6 +37,9 @@ entry: } ; FUNC-LABEL: {{^}}local_load_v3i64: +; SICIVI: s_mov_b32 m0 +; GFX9-NOT: m0 + ; GCN-DAG: ds_read2_b64 ; GCN-DAG: ds_read_b64 @@ -47,6 +57,9 @@ entry: } ; FUNC-LABEL: {{^}}local_load_v4i64: +; SICIVI: s_mov_b32 m0 +; GFX9-NOT: m0 + ; GCN: ds_read2_b64 ; GCN: ds_read2_b64 @@ -67,6 +80,9 @@ entry: } ; FUNC-LABEL: {{^}}local_load_v8i64: +; SICIVI: s_mov_b32 m0 +; GFX9-NOT: m0 + ; GCN: ds_read2_b64 ; GCN: ds_read2_b64 ; GCN: ds_read2_b64 @@ -96,6 +112,9 @@ entry: } ; FUNC-LABEL: {{^}}local_load_v16i64: +; SICIVI: s_mov_b32 m0 +; GFX9-NOT: m0 + ; GCN: ds_read2_b64 ; GCN: ds_read2_b64 ; GCN: ds_read2_b64 |
