diff options
| author | Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> | 2018-03-30 16:19:13 +0000 |
|---|---|---|
| committer | Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> | 2018-03-30 16:19:13 +0000 |
| commit | 74e2974ac6af988922c7bd2edf3c70531c03c798 (patch) | |
| tree | 0220bb5373b541614d821e78d4e10255cd964d94 /llvm/test/CodeGen/AMDGPU/llvm.sqrt.f16.ll | |
| parent | 0961218c109feac256c612f79a3d7c1249aef0f3 (diff) | |
| download | bcm5719-llvm-74e2974ac6af988922c7bd2edf3c70531c03c798.tar.gz bcm5719-llvm-74e2974ac6af988922c7bd2edf3c70531c03c798.zip | |
[AMDGPU] Fixed some instructions latencies
Differential Revision: https://reviews.llvm.org/D45073
llvm-svn: 328874
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/llvm.sqrt.f16.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/llvm.sqrt.f16.ll | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.sqrt.f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.sqrt.f16.ll index 48c82512466..1e00e09421d 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.sqrt.f16.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.sqrt.f16.ll @@ -24,13 +24,13 @@ entry: ; GCN-LABEL: {{^}}sqrt_v2f16 ; GCN: buffer_load_dword v[[A_V2_F16:[0-9]+]] -; SI: v_cvt_f32_f16_e32 v[[A_F32_0:[0-9]+]], v[[A_V2_F16]] ; SI: v_lshrrev_b32_e32 v[[A_F16_1:[0-9]+]], 16, v[[A_V2_F16]] ; SI: v_cvt_f32_f16_e32 v[[A_F32_1:[0-9]+]], v[[A_F16_1]] -; SI: v_sqrt_f32_e32 v[[R_F32_0:[0-9]+]], v[[A_F32_0]] -; SI: v_cvt_f16_f32_e32 v[[R_F16_0:[0-9]+]], v[[R_F32_0]] +; SI: v_cvt_f32_f16_e32 v[[A_F32_0:[0-9]+]], v[[A_V2_F16]] ; SI: v_sqrt_f32_e32 v[[R_F32_1:[0-9]+]], v[[A_F32_1]] +; SI: v_sqrt_f32_e32 v[[R_F32_0:[0-9]+]], v[[A_F32_0]] ; SI: v_cvt_f16_f32_e32 v[[R_F16_1:[0-9]+]], v[[R_F32_1]] +; SI: v_cvt_f16_f32_e32 v[[R_F16_0:[0-9]+]], v[[R_F32_0]] ; SI-DAG: v_lshlrev_b32_e32 v[[R_F16_HI:[0-9]+]], 16, v[[R_F16_1]] ; SI-NOT: v_and_b32 ; SI: v_or_b32_e32 v[[R_V2_F16:[0-9]+]], v[[R_F16_0]], v[[R_F16_HI]] |
