[AMDGPU] Ensure trig range reduction only used for subtargets that require it

Summary:
GFX9 and above support sin/cos instructions with a greater range and thus don't
require a fract instruction prior to invocation.

Added a subtarget feature to reflect this and added code to take advantage of
expanded range on GFX9+

Also updated the tests to check correct behaviour

Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, tpr, t-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D51933

Change-Id: I1c1f1d3726a5ae32116646ca5cfa1ab4ef69e5b0
llvm-svn: 342222

1 files changed, 52 insertions, 42 deletions

diff --git a/llvm/test/CodeGen/AMDGPU/llvm.sin.ll b/llvm/test/CodeGen/AMDGPU/llvm.sin.ll
index 2a17303267b..45b4e874da0 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.sin.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.sin.ll
@@ -1,5 +1,8 @@
 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
+; RUN: llc -march=amdgcn -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SICIVI,FUNC %s
+; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SICIVI,FUNC %s
+; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SICIVI,FUNC %s
+; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9,FUNC %s
 
 ; FUNC-LABEL: sin_f32
 ; EG: MULADD_IEEE *
@@ -8,10 +11,11 @@
 ; EG: SIN * T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
 ; EG-NOT: SIN
 
-; SI: v_mul_f32
-; SI: v_fract_f32
-; SI: v_sin_f32
-; SI-NOT: v_sin_f32
+; GCN: v_mul_f32
+; SICIVI: v_fract_f32
+; GFX9-NOT: v_fract_f32
+; GCN: v_sin_f32
+; GCN-NOT: v_sin_f32
 define amdgpu_kernel void @sin_f32(float addrspace(1)* %out, float %x) #1 {
    %sin = call float @llvm.sin.f32(float %x)
    store float %sin, float addrspace(1)* %out
@@ -19,11 +23,12 @@ define amdgpu_kernel void @sin_f32(float addrspace(1)* %out, float %x) #1 {
 }
 
 ; FUNC-LABEL: {{^}}safe_sin_3x_f32:
-; SI: v_mul_f32
-; SI: v_mul_f32
-; SI: v_fract_f32
-; SI: v_sin_f32
-; SI-NOT: v_sin_f32
+; GCN: v_mul_f32
+; GCN: v_mul_f32
+; SICIVI: v_fract_f32
+; GFX9-NOT: v_fract_f32
+; GCN: v_sin_f32
+; GCN-NOT: v_sin_f32
 define amdgpu_kernel void @safe_sin_3x_f32(float addrspace(1)* %out, float %x) #1 {
   %y = fmul float 3.0, %x
   %sin = call float @llvm.sin.f32(float %y)
@@ -32,12 +37,13 @@ define amdgpu_kernel void @safe_sin_3x_f32(float addrspace(1)* %out, float %x) #
 }
 
 ; FUNC-LABEL: {{^}}unsafe_sin_3x_f32:
-; SI-NOT: v_add_f32
-; SI: 0x3ef47644
-; SI: v_mul_f32
-; SI: v_fract_f32
-; SI: v_sin_f32
-; SI-NOT: v_sin_f32
+; GCN-NOT: v_add_f32
+; GCN: 0x3ef47644
+; GCN: v_mul_f32
+; SICIVI: v_fract_f32
+; GFX9-NOT: v_fract_f32
+; GCN: v_sin_f32
+; GCN-NOT: v_sin_f32
 define amdgpu_kernel void @unsafe_sin_3x_f32(float addrspace(1)* %out, float %x) #2 {
   %y = fmul float 3.0, %x
   %sin = call float @llvm.sin.f32(float %y)
@@ -46,11 +52,12 @@ define amdgpu_kernel void @unsafe_sin_3x_f32(float addrspace(1)* %out, float %x)
 }
 
 ; FUNC-LABEL: {{^}}safe_sin_2x_f32:
-; SI: v_add_f32
-; SI: v_mul_f32
-; SI: v_fract_f32
-; SI: v_sin_f32
-; SI-NOT: v_sin_f32
+; GCN: v_add_f32
+; GCN: v_mul_f32
+; SICIVI: v_fract_f32
+; GFX9-NOT: v_fract_f32
+; GCN: v_sin_f32
+; GCN-NOT: v_sin_f32
 define amdgpu_kernel void @safe_sin_2x_f32(float addrspace(1)* %out, float %x) #1 {
   %y = fmul float 2.0, %x
   %sin = call float @llvm.sin.f32(float %y)
@@ -59,12 +66,13 @@ define amdgpu_kernel void @safe_sin_2x_f32(float addrspace(1)* %out, float %x) #
 }
 
 ; FUNC-LABEL: {{^}}unsafe_sin_2x_f32:
-; SI-NOT: v_add_f32
-; SI: 0x3ea2f983
-; SI: v_mul_f32
-; SI: v_fract_f32
-; SI: v_sin_f32
-; SI-NOT: v_sin_f32
+; GCN-NOT: v_add_f32
+; GCN: 0x3ea2f983
+; GCN: v_mul_f32
+; SICIVI: v_fract_f32
+; GFX9-NOT: v_fract_f32
+; GCN: v_sin_f32
+; GCN-NOT: v_sin_f32
 define amdgpu_kernel void @unsafe_sin_2x_f32(float addrspace(1)* %out, float %x) #2 {
   %y = fmul float 2.0, %x
   %sin = call float @llvm.sin.f32(float %y)
@@ -73,11 +81,12 @@ define amdgpu_kernel void @unsafe_sin_2x_f32(float addrspace(1)* %out, float %x)
 }
 
 ; FUNC-LABEL: {{^}}test_safe_2sin_f32:
-; SI: v_add_f32
-; SI: v_mul_f32
-; SI: v_fract_f32
-; SI: v_sin_f32
-; SI-NOT: v_sin_f32
+; GCN: v_add_f32
+; GCN: v_mul_f32
+; SICIVI: v_fract_f32
+; GFX9-NOT: v_fract_f32
+; GCN: v_sin_f32
+; GCN-NOT: v_sin_f32
 define amdgpu_kernel void @test_safe_2sin_f32(float addrspace(1)* %out, float %x) #1 {
    %y = fmul float 2.0, %x
    %sin = call float @llvm.sin.f32(float %y)
@@ -86,11 +95,12 @@ define amdgpu_kernel void @test_safe_2sin_f32(float addrspace(1)* %out, float %x
 }
 
 ; FUNC-LABEL: {{^}}test_unsafe_2sin_f32:
-; SI: 0x3ea2f983
-; SI: v_mul_f32
-; SI: v_fract_f32
-; SI: v_sin_f32
-; SI-NOT: v_sin_f32
+; GCN: 0x3ea2f983
+; GCN: v_mul_f32
+; SICIVI: v_fract_f32
+; GFX9-NOT: v_fract_f32
+; GCN: v_sin_f32
+; GCN-NOT: v_sin_f32
 define amdgpu_kernel void @test_unsafe_2sin_f32(float addrspace(1)* %out, float %x) #2 {
    %y = fmul float 2.0, %x
    %sin = call float @llvm.sin.f32(float %y)
@@ -105,11 +115,11 @@ define amdgpu_kernel void @test_unsafe_2sin_f32(float addrspace(1)* %out, float
 ; EG: SIN * T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
 ; EG-NOT: SIN
 
-; SI: v_sin_f32
-; SI: v_sin_f32
-; SI: v_sin_f32
-; SI: v_sin_f32
-; SI-NOT: v_sin_f32
+; GCN: v_sin_f32
+; GCN: v_sin_f32
+; GCN: v_sin_f32
+; GCN: v_sin_f32
+; GCN-NOT: v_sin_f32
 define amdgpu_kernel void @sin_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %vx) #1 {
    %sin = call <4 x float> @llvm.sin.v4f32( <4 x float> %vx)
    store <4 x float> %sin, <4 x float> addrspace(1)* %out