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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-07-15 21:27:08 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-07-15 21:27:08 +0000 |
| commit | 82e5e1e564d77dcd8babbfa9c2850912f94786e4 (patch) | |
| tree | 81e53dcf93d1effa226d94c94967d4646f2cbcaa /llvm/test/CodeGen/AMDGPU/llvm.pow.ll | |
| parent | 11d3e21f2b7297ddcb213f6892134b5c8f2a520b (diff) | |
| download | bcm5719-llvm-82e5e1e564d77dcd8babbfa9c2850912f94786e4.tar.gz bcm5719-llvm-82e5e1e564d77dcd8babbfa9c2850912f94786e4.zip | |
AMDGPU: Fix TargetPrefix for remaining r600 intrinsics
llvm-svn: 275619
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/llvm.pow.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/llvm.pow.ll | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.pow.ll b/llvm/test/CodeGen/AMDGPU/llvm.pow.ll index 8d1381143ad..3f203ddf93b 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.pow.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.pow.ll @@ -10,7 +10,7 @@ define amdgpu_ps void @test1(<4 x float> inreg %reg0) { %r1 = extractelement <4 x float> %reg0, i32 1 %r2 = call float @llvm.pow.f32( float %r0, float %r1) %vec = insertelement <4 x float> undef, float %r2, i32 0 - call void @llvm.R600.store.swizzle(<4 x float> %vec, i32 0, i32 0) + call void @llvm.r600.store.swizzle(<4 x float> %vec, i32 0, i32 0) ret void } @@ -29,10 +29,10 @@ define amdgpu_ps void @test1(<4 x float> inreg %reg0) { ;CHECK-NEXT: EXP_IEEE * T{{[0-9]+\.[XYZW], PV\.[XYZW]}}, define amdgpu_ps void @test2(<4 x float> inreg %reg0, <4 x float> inreg %reg1) { %vec = call <4 x float> @llvm.pow.v4f32( <4 x float> %reg0, <4 x float> %reg1) - call void @llvm.R600.store.swizzle(<4 x float> %vec, i32 0, i32 0) + call void @llvm.r600.store.swizzle(<4 x float> %vec, i32 0, i32 0) ret void } declare float @llvm.pow.f32(float ,float ) readonly declare <4 x float> @llvm.pow.v4f32(<4 x float> ,<4 x float> ) readonly -declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) +declare void @llvm.r600.store.swizzle(<4 x float>, i32, i32) |
