diff options
| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-11-15 00:04:33 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-11-15 00:04:33 +0000 |
| commit | 972034bda9623c0a8441dae1d374c74137f85171 (patch) | |
| tree | 3829e1d7872ef19021f0fc364b4e682f62c22f2b /llvm/test/CodeGen/AMDGPU/llvm.cos.f16.ll | |
| parent | 9c884e495c83e73c4cc8768adc1572fcf582c08c (diff) | |
| download | bcm5719-llvm-972034bda9623c0a8441dae1d374c74137f85171.tar.gz bcm5719-llvm-972034bda9623c0a8441dae1d374c74137f85171.zip | |
AMDGPU: Fix formatting of 1/2pi immediate
llvm-svn: 286912
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/llvm.cos.f16.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/llvm.cos.f16.ll | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.cos.f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.cos.f16.ll index d2b85cfd933..bb3a5a4dea7 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.cos.f16.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.cos.f16.ll @@ -7,7 +7,7 @@ declare <2 x half> @llvm.cos.v2f16(<2 x half> %a) ; GCN-LABEL: {{^}}cos_f16 ; GCN: buffer_load_ushort v[[A_F16:[0-9]+]] ; GCN: v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]] -; GCN: v_mul_f32_e32 v[[M_F32:[0-9]+]], {{1/2pi|0x3e22f983}}, v[[A_F32]] +; GCN: v_mul_f32_e32 v[[M_F32:[0-9]+]], {{0.15915494|0x3e22f983}}, v[[A_F32]] ; GCN: v_fract_f32_e32 v[[F_F32:[0-9]+]], v[[M_F32]] ; GCN: v_cos_f32_e32 v[[R_F32:[0-9]+]], v[[F_F32]] ; GCN: v_cvt_f16_f32_e32 v[[R_F16:[0-9]+]], v[[R_F32]] @@ -30,10 +30,10 @@ entry: ; GCN: v_lshrrev_b32_e32 v[[A_F16_1:[0-9]+]], 16, v[[A_V2_F16]] ; GCN: v_cvt_f32_f16_e32 v[[A_F32_1:[0-9]+]], v[[A_F16_1]] ; SI: v_mul_f32_e32 v[[M_F32_0:[0-9]+]], v[[HALF_PIE]], v[[A_F32_0]] -; VI: v_mul_f32_e32 v[[M_F32_0:[0-9]+]], 1/2pi, v[[A_F32_0]] +; VI: v_mul_f32_e32 v[[M_F32_0:[0-9]+]], 0.15915494, v[[A_F32_0]] ; GCN: v_fract_f32_e32 v[[F_F32_0:[0-9]+]], v[[M_F32_0]] ; SI: v_mul_f32_e32 v[[M_F32_1:[0-9]+]], v[[HALF_PIE]], v[[A_F32_1]] -; VI: v_mul_f32_e32 v[[M_F32_1:[0-9]+]], 1/2pi, v[[A_F32_1]] +; VI: v_mul_f32_e32 v[[M_F32_1:[0-9]+]], 0.15915494, v[[A_F32_1]] ; GCN: v_fract_f32_e32 v[[F_F32_1:[0-9]+]], v[[M_F32_1]] ; GCN: v_cos_f32_e32 v[[R_F32_0:[0-9]+]], v[[F_F32_0]] ; GCN: v_cos_f32_e32 v[[R_F32_1:[0-9]+]], v[[F_F32_1]] |
