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| author | Tom Stellard <thomas.stellard@amd.com> | 2016-02-12 17:57:54 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2016-02-12 17:57:54 +0000 |
| commit | 46937ca4e7692dddfdd06f56bb4858ffec0c9279 (patch) | |
| tree | fb0f054e2a59e9f4ece11c183c186aab0d564b61 /llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workgroup.id.ll | |
| parent | e07f1aa8faffa4cbd71ec48b0f1de550c7f29816 (diff) | |
| download | bcm5719-llvm-46937ca4e7692dddfdd06f56bb4858ffec0c9279.tar.gz bcm5719-llvm-46937ca4e7692dddfdd06f56bb4858ffec0c9279.zip | |
[AMDGPU] Assembler: Swap operands of flat_store instructions to match AMD assembler
Historically, AMD internal sp3 assembler has flat_store* addr, data
format. To match existing code and to enable reuse, change LLVM
definitions to match. Also update MC and CodeGen tests.
Differential Revision: http://reviews.llvm.org/D16927
Patch by: Nikolay Haustov
llvm-svn: 260694
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workgroup.id.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workgroup.id.ll | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workgroup.id.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workgroup.id.ll index f9385761931..c22eac7e271 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workgroup.id.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workgroup.id.ll @@ -25,7 +25,7 @@ declare i32 @llvm.amdgcn.workgroup.id.z() #0 ; HSA: v_mov_b32_e32 [[VCOPY:v[0-9]+]], s6{{$}} ; ALL-NOT: [[VCOPY]] -; ALL: {{buffer|flat}}_store_dword [[VCOPY]] +; ALL: {{buffer|flat}}_store_dword {{.*}}[[VCOPY]] ; HSA: COMPUTE_PGM_RSRC2:USER_SGPR: 6 ; ALL-NOHSA: COMPUTE_PGM_RSRC2:USER_SGPR: 2 @@ -53,7 +53,7 @@ define void @test_workgroup_id_x(i32 addrspace(1)* %out) #1 { ; HSA: v_mov_b32_e32 [[VCOPY:v[0-9]+]], s7{{$}} ; ALL-NOT: [[VCOPY]] -; ALL: {{buffer|flat}}_store_dword [[VCOPY]] +; ALL: {{buffer|flat}}_store_dword {{.*}}[[VCOPY]] ; HSA: COMPUTE_PGM_RSRC2:USER_SGPR: 6 ; ALL-NOHSA: COMPUTE_PGM_RSRC2:USER_SGPR: 2 @@ -89,7 +89,7 @@ define void @test_workgroup_id_y(i32 addrspace(1)* %out) #1 { ; HSA: v_mov_b32_e32 [[VCOPY:v[0-9]+]], s7{{$}} ; ALL-NOT: [[VCOPY]] -; ALL: {{buffer|flat}}_store_dword [[VCOPY]] +; ALL: {{buffer|flat}}_store_dword {{.*}}[[VCOPY]] ; HSA: COMPUTE_PGM_RSRC2:USER_SGPR: 6 ; ALL-NOHSA: COMPUTE_PGM_RSRC2:USER_SGPR: 2 |
