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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2015-09-24 19:52:21 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2015-09-24 19:52:21 +0000 |
| commit | d6adfb401c5e9f7ec111866491ab3223d002a657 (patch) | |
| tree | 83c1afca31b791869f6e155ff30fac5361bba0e7 /llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.wbinvl1.sc.ll | |
| parent | c116767fecbaaea524ece01fe7cf59808db82c10 (diff) | |
| download | bcm5719-llvm-d6adfb401c5e9f7ec111866491ab3223d002a657.tar.gz bcm5719-llvm-d6adfb401c5e9f7ec111866491ab3223d002a657.zip | |
AMDGPU: Add cache invalidation instructions.
These are necessary for implementing mem_fence for
OpenCL 2.0.
The VI assembler tests are disabled since it seems to be
using the wrong encoding or opcode.
llvm-svn: 248532
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.wbinvl1.sc.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.wbinvl1.sc.ll | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.wbinvl1.sc.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.wbinvl1.sc.ll new file mode 100644 index 00000000000..746298465e5 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.wbinvl1.sc.ll @@ -0,0 +1,14 @@ +; RUN: llc -march=amdgcn -mcpu=tahiti -show-mc-encoding < %s | FileCheck -check-prefix=SI %s + +declare void @llvm.amdgcn.buffer.wbinvl1.sc() #0 + +; SI-LABEL: {{^}}test_buffer_wbinvl1_sc: +; SI-NEXT: ; BB#0: +; SI-NEXT: buffer_wbinvl1_sc ; encoding: [0x00,0x00,0xc0,0xe1,0x00,0x00,0x00,0x00] +; SI-NEXT: s_endpgm +define void @test_buffer_wbinvl1_sc() #0 { + call void @llvm.amdgcn.buffer.wbinvl1.sc() + ret void +} + +attributes #0 = { nounwind } |
