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| author | Tom Stellard <thomas.stellard@amd.com> | 2016-11-03 17:13:50 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2016-11-03 17:13:50 +0000 |
| commit | 2b3379cdffaa5d2af96abf0489f9755149be1f8e (patch) | |
| tree | 95c48ec395af390718e2900e4eed4bbefd0d257a /llvm/test/CodeGen/AMDGPU/llvm.AMDGPU.bfe.u32.ll | |
| parent | 40c15abe5fa31468f3ccc5c4439d29bb5e2e8c71 (diff) | |
| download | bcm5719-llvm-2b3379cdffaa5d2af96abf0489f9755149be1f8e.tar.gz bcm5719-llvm-2b3379cdffaa5d2af96abf0489f9755149be1f8e.zip | |
AMDGPU: Add VI i16 support
Patch By: Wei Ding
Differential Revision: https://reviews.llvm.org/D18049
llvm-svn: 285939
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/llvm.AMDGPU.bfe.u32.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/llvm.AMDGPU.bfe.u32.ll | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.AMDGPU.bfe.u32.ll b/llvm/test/CodeGen/AMDGPU/llvm.AMDGPU.bfe.u32.ll index 541119242a9..bf5d492dca4 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.AMDGPU.bfe.u32.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.AMDGPU.bfe.u32.ll @@ -1,5 +1,6 @@ -; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s -; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC -check-prefix=GCN %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=FUNC -check-prefix=GCN %s +; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=FUNC -check-prefix=GCN %s ; RUN: llc -march=r600 -mcpu=redwood -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s declare i32 @llvm.AMDGPU.bfe.u32(i32, i32, i32) nounwind readnone @@ -73,11 +74,14 @@ define void @bfe_u32_zextload_i8(i32 addrspace(1)* %out, i8 addrspace(1)* %in) n } ; FUNC-LABEL: {{^}}bfe_u32_zext_in_reg_i8: -; SI: buffer_load_dword +; GCN: buffer_load_dword ; SI: v_add_i32 ; SI-NEXT: v_and_b32_e32 +; FIXME: Should be using s_add_i32 +; VI: v_add_i32 +; VI-NEXT: v_and_b32_e32 ; SI-NOT: {{[^@]}}bfe -; SI: s_endpgm +; GCN: s_endpgm define void @bfe_u32_zext_in_reg_i8(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { %load = load i32, i32 addrspace(1)* %in, align 4 %add = add i32 %load, 1 |
