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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-03-21 21:39:51 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-03-21 21:39:51 +0000 |
| commit | 3dbeefa978fb7e7b231b249f9cd90c67b9e83277 (patch) | |
| tree | d74bf7fe30e44588d573919f3625edacb2586112 /llvm/test/CodeGen/AMDGPU/literals.ll | |
| parent | f6021ecddc73d14c94ad70938250d58f330795be (diff) | |
| download | bcm5719-llvm-3dbeefa978fb7e7b231b249f9cd90c67b9e83277.tar.gz bcm5719-llvm-3dbeefa978fb7e7b231b249f9cd90c67b9e83277.zip | |
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel
Currently the default C calling convention functions are treated
the same as compute kernels. Make this explicit so the default
calling convention can be changed to a non-kernel.
Converted with perl -pi -e 's/define void/define amdgpu_kernel void/'
on the relevant test directories (and undoing in one place that actually
wanted a non-kernel).
llvm-svn: 298444
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/literals.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/literals.ll | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/literals.ll b/llvm/test/CodeGen/AMDGPU/literals.ll index 82fbb7f4618..1c546ba9f74 100644 --- a/llvm/test/CodeGen/AMDGPU/literals.ll +++ b/llvm/test/CodeGen/AMDGPU/literals.ll @@ -10,7 +10,7 @@ ; CHECK: LSHR ; CHECK-NEXT: ADD_INT * {{\** *}}T{{[0-9]\.[XYZW]}}, KC0[2].Z, literal.y ; CHECK-NEXT: 5 -define void @i32_literal(i32 addrspace(1)* %out, i32 %in) { +define amdgpu_kernel void @i32_literal(i32 addrspace(1)* %out, i32 %in) { entry: %0 = add i32 5, %in store i32 %0, i32 addrspace(1)* %out @@ -27,7 +27,7 @@ entry: ; CHECK: LSHR ; CHECK-NEXT: ADD * {{\** *}}T{{[0-9]\.[XYZW]}}, KC0[2].Z, literal.y ; CHECK-NEXT: 1084227584(5.0 -define void @float_literal(float addrspace(1)* %out, float %in) { +define amdgpu_kernel void @float_literal(float addrspace(1)* %out, float %in) { entry: %0 = fadd float 5.0, %in store float %0, float addrspace(1)* %out @@ -41,7 +41,7 @@ entry: ; CHECK-NEXT: MOV {{\** *}}T[[GPR]].Z, 0.0 ; CHECK-NEXT: MOV {{\** *}}T[[GPR]].W, 0.0 -define void @inline_literal_reg_sequence(<4 x i32> addrspace(1)* %out) { +define amdgpu_kernel void @inline_literal_reg_sequence(<4 x i32> addrspace(1)* %out) { entry: store <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> addrspace(1)* %out ret void @@ -52,7 +52,7 @@ entry: ; CHECK-NEXT: DOT4 T[[GPR]].Y (MASKED), 1.0 ; CHECK-NEXT: DOT4 T[[GPR]].Z (MASKED), 1.0 ; CHECK-NEXT: DOT4 * T[[GPR]].W (MASKED), 1.0 -define void @inline_literal_dot4(float addrspace(1)* %out) { +define amdgpu_kernel void @inline_literal_dot4(float addrspace(1)* %out) { entry: %0 = call float @llvm.r600.dot4(<4 x float> <float 1.0, float 1.0, float 1.0, float 1.0>, <4 x float> <float 1.0, float 1.0, float 1.0, float 1.0>) store float %0, float addrspace(1)* %out |
