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author | Francis Visoiu Mistrih <francisvm@yahoo.com> | 2017-11-30 12:12:19 +0000 |
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committer | Francis Visoiu Mistrih <francisvm@yahoo.com> | 2017-11-30 12:12:19 +0000 |
commit | 93ef145862e140ed880fd2eca404dc2641a12093 (patch) | |
tree | 6e29f9874fc995008ef8e53a6375b06de67d33e6 /llvm/test/CodeGen/AMDGPU/lds-output-queue.ll | |
parent | bfb8fa5a160a943d9cf8d7254cf4375f2c135f2d (diff) | |
download | bcm5719-llvm-93ef145862e140ed880fd2eca404dc2641a12093.tar.gz bcm5719-llvm-93ef145862e140ed880fd2eca404dc2641a12093.zip |
[CodeGen] Print "%vreg0" as "%0" in both MIR and debug output
As part of the unification of the debug format and the MIR format, avoid
printing "vreg" for virtual registers (which is one of the current MIR
possibilities).
Basically:
* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E "s/%vreg([0-9]+)/%\1/g"
* grep -nr '%vreg' . and fix if needed
* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E "s/ vreg([0-9]+)/ %\1/g"
* grep -nr 'vreg[0-9]\+' . and fix if needed
Differential Revision: https://reviews.llvm.org/D40420
llvm-svn: 319427
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/lds-output-queue.ll')
-rw-r--r-- | llvm/test/CodeGen/AMDGPU/lds-output-queue.ll | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/lds-output-queue.ll b/llvm/test/CodeGen/AMDGPU/lds-output-queue.ll index e5df12a1e5a..f8fb12eefa6 100644 --- a/llvm/test/CodeGen/AMDGPU/lds-output-queue.ll +++ b/llvm/test/CodeGen/AMDGPU/lds-output-queue.ll @@ -46,20 +46,20 @@ declare void @llvm.r600.group.barrier() nounwind convergent ; ; The instruction selection phase will generate ISA that looks like this: ; %oqap = LDS_READ_RET -; %vreg0 = MOV %oqap -; %vreg1 = VTX_READ_32 -; %vreg2 = ADD_INT %vreg1, %vreg0 +; %0 = MOV %oqap +; %1 = VTX_READ_32 +; %2 = ADD_INT %1, %0 ; ; The bottom scheduler will schedule the two ALU instructions first: ; ; UNSCHEDULED: ; %oqap = LDS_READ_RET -; %vreg1 = VTX_READ_32 +; %1 = VTX_READ_32 ; ; SCHEDULED: ; -; vreg0 = MOV %oqap -; vreg2 = ADD_INT %vreg1, %vreg2 +; %0 = MOV %oqap +; %2 = ADD_INT %1, %2 ; ; The lack of proper aliasing results in the local memory read (LDS_READ_RET) ; to consider the global memory read (VTX_READ_32) has a chain dependency, so @@ -69,10 +69,10 @@ declare void @llvm.r600.group.barrier() nounwind convergent ; Alu clause: ; %oqap = LDS_READ_RET ; VTX clause: -; %vreg1 = VTX_READ_32 +; %1 = VTX_READ_32 ; Alu clause: -; vreg0 = MOV %oqap -; vreg2 = ADD_INT %vreg1, %vreg2 +; %0 = MOV %oqap +; %2 = ADD_INT %1, %2 ; ; This is an illegal program because the oqap def and use know occur in ; different ALU clauses. |