AMDGPU: Add test for m0 initialization in basic loop

Initialization of m0 is emitted for each LDS operation, so
every block with LDS usage ends up with one. MachineLICM
used to fail to hoist this out of the loop, so every loop
iteration with LDS usage in it would re-initialize it.

This seems to be fixed now, so add a test to make sure that
it stays this way.

llvm-svn: 266156

1 files changed, 48 insertions, 0 deletions

diff --git a/llvm/test/CodeGen/AMDGPU/lds-m0-init-in-loop.ll b/llvm/test/CodeGen/AMDGPU/lds-m0-init-in-loop.ll
new file mode 100644
index 00000000000..d3628a0c91b
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/lds-m0-init-in-loop.ll
@@ -0,0 +1,48 @@
+; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
+
+; Make sure that m0 is not reinitialized in the loop.
+
+; GCN-LABEL: {{^}}copy_local_to_global_loop_m0_init:
+; GCN: s_cbranch_scc1 BB0_2
+
+; Initialize in preheader
+; GCN: s_mov_b32 m0, -1
+
+; GCN: BB0_3:
+; GCN: ds_read_b32
+; GCN: buffer_store_dword
+
+; GCN: s_cbranch_vccnz BB0_2
+; GCN: s_branch BB0_3
+
+; GCN: BB0_2:
+; GCN-NEXT: s_endpgm
+define void @copy_local_to_global_loop_m0_init(i32 addrspace(1)* noalias nocapture %out, i32 addrspace(3)* noalias nocapture readonly %in, i32 %n) #0 {
+bb:
+  %tmp = icmp sgt i32 %n, 0
+  br i1 %tmp, label %.lr.ph.preheader, label %._crit_edge
+
+.lr.ph.preheader:                                 ; preds = %bb
+  br label %.lr.ph
+
+._crit_edge.loopexit:                             ; preds = %.lr.ph
+  br label %._crit_edge
+
+._crit_edge:                                      ; preds = %._crit_edge.loopexit, %bb
+  ret void
+
+.lr.ph:                                           ; preds = %.lr.ph, %.lr.ph.preheader
+  %indvars.iv = phi i64 [ %indvars.iv.next, %.lr.ph ], [ 0, %.lr.ph.preheader ]
+  %i.01 = phi i32 [ %tmp4, %.lr.ph ], [ 0, %.lr.ph.preheader ]
+  %tmp1 = getelementptr inbounds i32, i32 addrspace(3)* %in, i32 %i.01
+  %tmp2 = load i32, i32 addrspace(3)* %tmp1, align 4
+  %tmp3 = getelementptr inbounds i32, i32 addrspace(1)* %out, i64 %indvars.iv
+  store i32 %tmp2, i32 addrspace(1)* %tmp3, align 4
+  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
+  %tmp4 = add nuw nsw i32 %i.01, 1
+  %lftr.wideiv = trunc i64 %indvars.iv.next to i32
+  %exitcond = icmp eq i32 %lftr.wideiv, %n
+  br i1 %exitcond, label %._crit_edge.loopexit, label %.lr.ph
+}
+
+attributes #0 = { nounwind }