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| author | Tom Stellard <thomas.stellard@amd.com> | 2016-04-30 00:23:06 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2016-04-30 00:23:06 +0000 |
| commit | cb6ba62d6fce87cc28a5076ccebe05b740d2340d (patch) | |
| tree | a090c0340339618f28dbb530f14c77b5c572588d /llvm/test/CodeGen/AMDGPU/invariant-load-no-alias-store.ll | |
| parent | 52c68bb0f57fd53e4bd3f721e5fd4ca19544551f (diff) | |
| download | bcm5719-llvm-cb6ba62d6fce87cc28a5076ccebe05b740d2340d.tar.gz bcm5719-llvm-cb6ba62d6fce87cc28a5076ccebe05b740d2340d.zip | |
AMDGPU/SI: Enable the post-ra scheduler
Summary:
This includes a hazard recognizer implementation to replace some of
the hazard handling we had during frame index elimination.
Reviewers: arsenm
Subscribers: qcolombet, arsenm, llvm-commits
Differential Revision: http://reviews.llvm.org/D18602
llvm-svn: 268143
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/invariant-load-no-alias-store.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/invariant-load-no-alias-store.ll | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/invariant-load-no-alias-store.ll b/llvm/test/CodeGen/AMDGPU/invariant-load-no-alias-store.ll index a70da5be5f5..347170f79e3 100644 --- a/llvm/test/CodeGen/AMDGPU/invariant-load-no-alias-store.ll +++ b/llvm/test/CodeGen/AMDGPU/invariant-load-no-alias-store.ll @@ -7,8 +7,8 @@ ; from constant/invariant memory. ; GCN-LABEL: {{^}}test_merge_store_constant_i16_invariant_global_pointer_load: -; GCN: buffer_load_dwordx2 [[PTR:v\[[0-9]+:[0-9]+\]]], -; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 0x1c8007b +; GCN-DAG: buffer_load_dwordx2 [[PTR:v\[[0-9]+:[0-9]+\]]], +; GCN-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 0x1c8007b ; GCN: buffer_store_dword [[K]], [[PTR]] define void @test_merge_store_constant_i16_invariant_global_pointer_load(i16 addrspace(1)* addrspace(1)* dereferenceable(4096) nonnull %in) #0 { %ptr = load i16 addrspace(1)*, i16 addrspace(1)* addrspace(1)* %in, !invariant.load !0 |
