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| author | Tom Stellard <thomas.stellard@amd.com> | 2015-06-13 03:28:10 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2015-06-13 03:28:10 +0000 |
| commit | 45bb48ea197fe496865387120c7c55b56f0717d6 (patch) | |
| tree | 3914fb8c4ace9ea4dee024fc944d51dc45adf401 /llvm/test/CodeGen/AMDGPU/insert_subreg.ll | |
| parent | 8fa9677d4eb1cd43973eb59acc12b0534691d604 (diff) | |
| download | bcm5719-llvm-45bb48ea197fe496865387120c7c55b56f0717d6.tar.gz bcm5719-llvm-45bb48ea197fe496865387120c7c55b56f0717d6.zip | |
R600 -> AMDGPU rename
llvm-svn: 239657
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/insert_subreg.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/insert_subreg.ll | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/insert_subreg.ll b/llvm/test/CodeGen/AMDGPU/insert_subreg.ll new file mode 100644 index 00000000000..4a5e8869c2d --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/insert_subreg.ll @@ -0,0 +1,16 @@ +; RUN: llc -march=amdgcn -mcpu=SI -mattr=-promote-alloca -verify-machineinstrs < %s +; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-promote-alloca -verify-machineinstrs < %s + +; Test that INSERT_SUBREG instructions don't have non-register operands after +; instruction selection. + +; Make sure this doesn't crash +; CHECK-LABEL: test: +define void @test(i64 addrspace(1)* %out) { +entry: + %tmp0 = alloca [16 x i32] + %tmp1 = ptrtoint [16 x i32]* %tmp0 to i32 + %tmp2 = sext i32 %tmp1 to i64 + store i64 %tmp2, i64 addrspace(1)* %out + ret void +} |
