diff options
| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-11-24 00:26:40 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-11-24 00:26:40 +0000 |
| commit | 9e5c7b10316aca49605dd7cf5f4e6e4a3ab76cd6 (patch) | |
| tree | b163ccaf77708f0e9a1e3082c207e49e2d8b6d7b /llvm/test/CodeGen/AMDGPU/inline-constraints.ll | |
| parent | 8812f28f47a74d32bdd14181ebfe906cbfcd7346 (diff) | |
| download | bcm5719-llvm-9e5c7b10316aca49605dd7cf5f4e6e4a3ab76cd6.tar.gz bcm5719-llvm-9e5c7b10316aca49605dd7cf5f4e6e4a3ab76cd6.zip | |
AMDGPU: Make m0 unallocatable
m0 may need to be written for spill code, so
we don't want general code uses relying on the
value stored in it.
This introduces a few code quality regressions where copies
from m0 are not coalesced into copies of a copy of m0.
llvm-svn: 287841
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/inline-constraints.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/inline-constraints.ll | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/inline-constraints.ll b/llvm/test/CodeGen/AMDGPU/inline-constraints.ll index 3c0bb75a607..1bcbd14009c 100644 --- a/llvm/test/CodeGen/AMDGPU/inline-constraints.ll +++ b/llvm/test/CodeGen/AMDGPU/inline-constraints.ll @@ -22,10 +22,11 @@ entry: ret void } +; FIXME: Should be able to avoid copy ; GCN-LABEL: {{^}}inline_sreg_constraint_m0: ; GCN: s_mov_b32 m0, -1 -; GCN-NOT: s_mov_b32 s{{[0-9]+}}, m0 -; GCN: ; use m0 +; GCN: s_mov_b32 [[COPY_M0:s[0-9]+]], m0 +; GCN: ; use [[COPY_M0]] define void @inline_sreg_constraint_m0() { %m0 = tail call i32 asm sideeffect "s_mov_b32 m0, -1", "={M0}"() tail call void asm sideeffect "; use $0", "s"(i32 %m0) |
