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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-07-06 20:57:05 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-07-06 20:57:05 +0000 |
| commit | 9aa45f047f303b6484afce6716472b3b1f510c7e (patch) | |
| tree | d25023848a172579a8d26d9860316edaffcee5d0 /llvm/test/CodeGen/AMDGPU/inline-asm.ll | |
| parent | a81198d82de20e14efce44826e302785bfda093a (diff) | |
| download | bcm5719-llvm-9aa45f047f303b6484afce6716472b3b1f510c7e.tar.gz bcm5719-llvm-9aa45f047f303b6484afce6716472b3b1f510c7e.zip | |
AMDGPU: Add macro fusion schedule DAG mutation
Try to increase opportunities to shrink vcc uses.
llvm-svn: 307313
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/inline-asm.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/inline-asm.ll | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/inline-asm.ll b/llvm/test/CodeGen/AMDGPU/inline-asm.ll index c0f5218efc1..75826d530cb 100644 --- a/llvm/test/CodeGen/AMDGPU/inline-asm.ll +++ b/llvm/test/CodeGen/AMDGPU/inline-asm.ll @@ -222,9 +222,9 @@ entry: ; FIXME: Should be scheduled to shrink vcc ; CHECK-LABEL: {{^}}i1_input_phys_vgpr_x2: ; CHECK: v_cmp_eq_u32_e32 vcc, 1, v0 -; CHECK: v_cmp_eq_u32_e64 s[0:1], 1, v1 ; CHECK: v_cndmask_b32_e64 v0, 0, -1, vcc -; CHECK: v_cndmask_b32_e64 v1, 0, -1, s[0:1] +; CHECK: v_cmp_eq_u32_e32 vcc, 1, v1 +; CHECK: v_cndmask_b32_e64 v1, 0, -1, vcc define amdgpu_kernel void @i1_input_phys_vgpr_x2() { entry: %val0 = load volatile i1, i1 addrspace(1)* undef |
