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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-07-19 13:57:44 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-07-19 13:57:44 +0000 |
| commit | 1022c0dfde51a32c31cb912ccf8256e60debebfd (patch) | |
| tree | 2b9ac120eff33333517f204fd68c9b81f7e66398 /llvm/test/CodeGen/AMDGPU/implicit-def-muse.ll | |
| parent | 8bb8915d43fe687237f31014f34fc6f2f79fb5ff (diff) | |
| download | bcm5719-llvm-1022c0dfde51a32c31cb912ccf8256e60debebfd.tar.gz bcm5719-llvm-1022c0dfde51a32c31cb912ccf8256e60debebfd.zip | |
AMDGPU: Decompose all values to 32-bit pieces for calling conventions
This is the more natural lowering, and presents more opportunities to
reduce 64-bit ops to 32-bit.
This should also help avoid issues graphics shaders have had with
64-bit values, and simplify argument lowering in globalisel.
llvm-svn: 366578
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/implicit-def-muse.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/implicit-def-muse.ll | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/implicit-def-muse.ll b/llvm/test/CodeGen/AMDGPU/implicit-def-muse.ll index fb540c3a6ba..4e0b342a75c 100644 --- a/llvm/test/CodeGen/AMDGPU/implicit-def-muse.ll +++ b/llvm/test/CodeGen/AMDGPU/implicit-def-muse.ll @@ -1,10 +1,11 @@ ; RUN: llc -march=amdgcn -stop-after=amdgpu-isel -verify-machineinstrs -o - %s | FileCheck %s ; CHECK-LABEL: vcopy_i1_undef -; CHECK: IMPLICIT_DEF -; CHECK-NOT: COPY -; CHECK: IMPLICIT_DEF +; CHECK: [[IMPDEF0:%[0-9]+]]:vreg_1 = IMPLICIT_DEF ; CHECK-NOT: COPY +; CHECK: [[IMPDEF1:%[0-9]+]]:vreg_1 = IMPLICIT_DEF +; CHECK-NOT: COPY [[IMPDEF0]] +; CHECK-NOT: COPY [[IMPDEF1]] ; CHECK: .false: define <2 x float> @vcopy_i1_undef(<2 x float> addrspace(1)* %p) { entry: |
