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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2015-11-30 21:16:03 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2015-11-30 21:16:03 +0000 |
| commit | 26f8f3db39f8fd856cfdce0689c5e5b84536eb9a (patch) | |
| tree | a7241314f78b6bf81416571bf7b298cd29b6a884 /llvm/test/CodeGen/AMDGPU/hsa.ll | |
| parent | ac234b604da563cbe53364116cf84abe4abbdb04 (diff) | |
| download | bcm5719-llvm-26f8f3db39f8fd856cfdce0689c5e5b84536eb9a.tar.gz bcm5719-llvm-26f8f3db39f8fd856cfdce0689c5e5b84536eb9a.zip | |
AMDGPU: Rework how private buffer passed for HSA
If we know we have stack objects, we reserve the registers
that the private buffer resource and wave offset are passed
and use them directly.
If not, reserve the last 5 SGPRs just in case we need to spill.
After register allocation, try to pick the next available registers
instead of the last SGPRs, and then insert copies from the inputs
to the reserved registers in the progloue.
This also only selectively enables all of the input registers
which are really required instead of always enabling them.
llvm-svn: 254331
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/hsa.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/hsa.ll | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/hsa.ll b/llvm/test/CodeGen/AMDGPU/hsa.ll index ab87fdbc00d..d9bb586163d 100644 --- a/llvm/test/CodeGen/AMDGPU/hsa.ll +++ b/llvm/test/CodeGen/AMDGPU/hsa.ll @@ -38,8 +38,10 @@ ; HSA: .amdgpu_hsa_kernel simple ; HSA: {{^}}simple: ; HSA: .amd_kernel_code_t +; HSA: enable_sgpr_private_segment_buffer = 1 +; HSA: enable_sgpr_kernarg_segment_ptr = 1 ; HSA: .end_amd_kernel_code_t -; HSA: s_load_dwordx2 s[{{[0-9]+:[0-9]+}}], s[0:1], 0x0 +; HSA: s_load_dwordx2 s[{{[0-9]+:[0-9]+}}], s[4:5], 0x0 ; Make sure we are setting the ATC bit: ; HSA-CI: s_mov_b32 s[[HI:[0-9]]], 0x100f000 |
