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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-04-14 21:58:15 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-04-14 21:58:15 +0000 |
| commit | 4ac341c8b31ab34c7cb90eda91a91e78a11a8baf (patch) | |
| tree | 195717ee1a4094630e5031af4dcf161e748169f8 /llvm/test/CodeGen/AMDGPU/fneg.f64.ll | |
| parent | 7900334dd530416b70fb04c8abb6f8c2c65da86d (diff) | |
| download | bcm5719-llvm-4ac341c8b31ab34c7cb90eda91a91e78a11a8baf.tar.gz bcm5719-llvm-4ac341c8b31ab34c7cb90eda91a91e78a11a8baf.zip | |
AMDGPU: Directly emit m0 initialization with s_mov_b32
Currently what comes out of instruction selection is a
register initialized to -1, and then copied to m0.
MachineCSE doesn't consider copies, but we want these
to be CSEed. This isn't much of a problem currently,
because SIFoldOperands is run immediately after.
This avoids regressions when SIFoldOperands is run later
from leaving all copies to m0.
llvm-svn: 266377
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/fneg.f64.ll')
0 files changed, 0 insertions, 0 deletions
