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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-01-12 18:48:09 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-01-12 18:48:09 +0000 |
| commit | 31c039ef2e16a85cd5ac15defabfaf9ddcd50f60 (patch) | |
| tree | 8400fa174f41b53b7b689e018a74c63fc9bb54ff /llvm/test/CodeGen/AMDGPU/fneg-combines.ll | |
| parent | 555e5980a5c7037fba5b40e8bab556a17e272511 (diff) | |
| download | bcm5719-llvm-31c039ef2e16a85cd5ac15defabfaf9ddcd50f60.tar.gz bcm5719-llvm-31c039ef2e16a85cd5ac15defabfaf9ddcd50f60.zip | |
AMDGPU: Fold free fneg into sin
llvm-svn: 291790
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/fneg-combines.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/fneg-combines.ll | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/fneg-combines.ll b/llvm/test/CodeGen/AMDGPU/fneg-combines.ll index c09b7e1fcde..d555d8d871d 100644 --- a/llvm/test/CodeGen/AMDGPU/fneg-combines.ll +++ b/llvm/test/CodeGen/AMDGPU/fneg-combines.ll @@ -1229,9 +1229,51 @@ define void @v_fneg_mul_legacy_multi_use_fneg_x_f32(float addrspace(1)* %out, fl ret void } +; -------------------------------------------------------------------------------- +; sin tests +; -------------------------------------------------------------------------------- + +; GCN-LABEL: {{^}}v_fneg_sin_f32: +; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]] +; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 0x3e22f983 +; GCN: v_mul_f32_e64 [[MUL:v[0-9]+]], [[K]], -[[A]] +; GCN: v_fract_f32_e32 [[FRACT:v[0-9]+]], [[MUL]] +; GCN: v_sin_f32_e32 [[RESULT:v[0-9]+]], [[FRACT]] +; GCN: buffer_store_dword [[RESULT]] +define void @v_fneg_sin_f32(float addrspace(1)* %out, float addrspace(1)* %a.ptr) #0 { + %tid = call i32 @llvm.amdgcn.workitem.id.x() + %tid.ext = sext i32 %tid to i64 + %a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext + %out.gep = getelementptr inbounds float, float addrspace(1)* %out, i64 %tid.ext + %a = load volatile float, float addrspace(1)* %a.gep + %sin = call float @llvm.sin.f32(float %a) + %fneg = fsub float -0.000000e+00, %sin + store float %fneg, float addrspace(1)* %out.gep + ret void +} + +; GCN-LABEL: {{^}}v_fneg_amdgcn_sin_f32: +; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]] +; GCN: v_sin_f32_e64 [[RESULT:v[0-9]+]], -[[A]] +; GCN: buffer_store_dword [[RESULT]] +define void @v_fneg_amdgcn_sin_f32(float addrspace(1)* %out, float addrspace(1)* %a.ptr) #0 { + %tid = call i32 @llvm.amdgcn.workitem.id.x() + %tid.ext = sext i32 %tid to i64 + %a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext + %out.gep = getelementptr inbounds float, float addrspace(1)* %out, i64 %tid.ext + %a = load volatile float, float addrspace(1)* %a.gep + %sin = call float @llvm.amdgcn.sin.f32(float %a) + %fneg = fsub float -0.000000e+00, %sin + store float %fneg, float addrspace(1)* %out.gep + ret void +} + declare i32 @llvm.amdgcn.workitem.id.x() #1 declare float @llvm.fma.f32(float, float, float) #1 declare float @llvm.fmuladd.f32(float, float, float) #1 +declare float @llvm.sin.f32(float) #1 + +declare float @llvm.amdgcn.sin.f32(float) #1 declare float @llvm.amdgcn.rcp.f32(float) #1 declare float @llvm.amdgcn.rcp.legacy(float) #1 declare float @llvm.amdgcn.fmul.legacy(float, float) #1 |
