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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-11-12 23:53:44 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-11-12 23:53:44 +0000 |
| commit | 70b92820158781ae42d89568b15873e74871e59f (patch) | |
| tree | f0a6777fcde991b0bdef4098ec26b986c134d8c4 /llvm/test/CodeGen/AMDGPU/fabs.f16.ll | |
| parent | cf9b6d8d578aa05ca47a6a27b6cb03a4c03a688c (diff) | |
| download | bcm5719-llvm-70b92820158781ae42d89568b15873e74871e59f.tar.gz bcm5719-llvm-70b92820158781ae42d89568b15873e74871e59f.zip | |
AMDGPU: Fix -enable-var-scope violations
llvm-svn: 318004
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/fabs.f16.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/fabs.f16.ll | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/fabs.f16.ll b/llvm/test/CodeGen/AMDGPU/fabs.f16.ll index 4429cfa7b8a..3e2b44fe905 100644 --- a/llvm/test/CodeGen/AMDGPU/fabs.f16.ll +++ b/llvm/test/CodeGen/AMDGPU/fabs.f16.ll @@ -1,6 +1,6 @@ -; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=CI %s -; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s -; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx901 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 %s +; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=CI %s +; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=tonga -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=VI %s +; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx901 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=GFX9 %s ; DAGCombiner will transform: ; (fabs (f16 bitcast (i16 a))) => (f16 bitcast (and (i16 a), 0x7FFFFFFF)) @@ -20,7 +20,7 @@ define amdgpu_kernel void @s_fabs_free_f16(half addrspace(1)* %out, i16 %in) { ; GCN-LABEL: {{^}}s_fabs_f16: ; CI: flat_load_ushort [[VAL:v[0-9]+]], -; CI: v_and_b32_e32 [[CVT0:v[0-9]+]], 0x7fff, [[VAL]] +; CI: v_and_b32_e32 [[RESULT:v[0-9]+]], 0x7fff, [[VAL]] ; CI: flat_store_short v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]] define amdgpu_kernel void @s_fabs_f16(half addrspace(1)* %out, half %in) { %fabs = call half @llvm.fabs.f16(half %in) |
