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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-10-20 17:44:17 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-10-20 17:44:17 +0000 |
| commit | e5be543a55986e353d40d79702eef5cff3934348 (patch) | |
| tree | a814a2a17aeabdb1314b14297ddb0da5779ffa42 /llvm/test/CodeGen/AMDGPU/ds-negative-offset-addressing-mode-loop.ll | |
| parent | 7cd57dcd5b716dd1dab446974abd4c51d01038a7 (diff) | |
| download | bcm5719-llvm-e5be543a55986e353d40d79702eef5cff3934348.tar.gz bcm5719-llvm-e5be543a55986e353d40d79702eef5cff3934348.zip | |
AMDGPU: Increase vcc liveness scan threshold
Avoids a test regression in a future patch. Also add debug printing on
this case, so I waste less time debugging folds in the future.
llvm-svn: 375367
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/ds-negative-offset-addressing-mode-loop.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/ds-negative-offset-addressing-mode-loop.ll | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/ds-negative-offset-addressing-mode-loop.ll b/llvm/test/CodeGen/AMDGPU/ds-negative-offset-addressing-mode-loop.ll index e2c7f1c47cf..5997e27fd81 100644 --- a/llvm/test/CodeGen/AMDGPU/ds-negative-offset-addressing-mode-loop.ll +++ b/llvm/test/CodeGen/AMDGPU/ds-negative-offset-addressing-mode-loop.ll @@ -7,8 +7,6 @@ declare void @llvm.amdgcn.s.barrier() #1 ; Function Attrs: nounwind ; CHECK-LABEL: {{^}}signed_ds_offset_addressing_loop: -; SI: s_movk_i32 [[K_0X88:s[0-9]+]], 0x -; SI: s_movk_i32 [[K_0X100:s[0-9]+]], 0x100 ; CHECK: BB0_1: ; CHECK: v_add_i32_e32 [[VADDR:v[0-9]+]], ; SI-DAG: ds_read_b32 v{{[0-9]+}}, [[VADDR]] @@ -16,9 +14,9 @@ declare void @llvm.amdgcn.s.barrier() #1 ; SI-DAG: ds_read_b32 v{{[0-9]+}}, [[VADDR8]] ; SI-DAG: v_add_i32_e32 [[VADDR0x80:v[0-9]+]], vcc, 0x80, [[VADDR]] ; SI-DAG: ds_read_b32 v{{[0-9]+}}, [[VADDR0x80]] -; SI-DAG: v_add_i32_e32 [[VADDR0x88:v[0-9]+]], vcc, [[K_0X88]], [[VADDR]] +; SI-DAG: v_add_i32_e32 [[VADDR0x88:v[0-9]+]], vcc, 0x88, [[VADDR]] ; SI-DAG: ds_read_b32 v{{[0-9]+}}, [[VADDR0x88]] -; SI-DAG: v_add_i32_e32 [[VADDR0x100:v[0-9]+]], vcc, [[K_0X100]], [[VADDR]] +; SI-DAG: v_add_i32_e32 [[VADDR0x100:v[0-9]+]], vcc, 0x100, [[VADDR]] ; SI-DAG: ds_read_b32 v{{[0-9]+}}, [[VADDR0x100]] ; CI-DAG: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, [[VADDR]] offset1:2 |
