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| author | Matthias Braun <matze@braunis.de> | 2016-08-24 01:32:41 +0000 |
|---|---|---|
| committer | Matthias Braun <matze@braunis.de> | 2016-08-24 01:32:41 +0000 |
| commit | 79f85b3b8ff8e54e9c94870477f2868929e481b7 (patch) | |
| tree | 67b36c04f6c3f2f4f73e0361a42cf993bb619d41 /llvm/test/CodeGen/AMDGPU/detect-dead-lanes.mir | |
| parent | b31163136ca249127b95a457308c7de3cb7a9841 (diff) | |
| download | bcm5719-llvm-79f85b3b8ff8e54e9c94870477f2868929e481b7.tar.gz bcm5719-llvm-79f85b3b8ff8e54e9c94870477f2868929e481b7.zip | |
MIRParser/MIRPrinter: Compute isSSA instead of printing/parsing it.
Specifying isSSA is an extra line at best and results in invalid MI at
worst. Compute the value instead.
Differential Revision: http://reviews.llvm.org/D22722
llvm-svn: 279600
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/detect-dead-lanes.mir')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/detect-dead-lanes.mir | 9 |
1 files changed, 0 insertions, 9 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/detect-dead-lanes.mir b/llvm/test/CodeGen/AMDGPU/detect-dead-lanes.mir index 9f776e0e572..057c663036c 100644 --- a/llvm/test/CodeGen/AMDGPU/detect-dead-lanes.mir +++ b/llvm/test/CodeGen/AMDGPU/detect-dead-lanes.mir @@ -26,7 +26,6 @@ # CHECK: S_NOP 0, implicit %4.sub1 # CHECK: S_NOP 0, implicit undef %5.sub0 name: test0 -isSSA: true registers: - { id: 0, class: sreg_32 } - { id: 1, class: sreg_32 } @@ -84,7 +83,6 @@ body: | # CHECK: %10 = EXTRACT_SUBREG undef %0, {{[0-9]+}} # CHECK: S_NOP 0, implicit undef %10 name: test1 -isSSA: true registers: - { id: 0, class: sreg_128 } - { id: 1, class: sreg_128 } @@ -163,7 +161,6 @@ body: | # CHECK: S_NOP 0, implicit %16.sub1 name: test2 -isSSA: true registers: - { id: 0, class: sreg_32 } - { id: 1, class: sreg_32 } @@ -221,7 +218,6 @@ body: | # CHECK: %1 = COPY %vcc # CHECK: S_NOP 0, implicit %1 name: test3 -isSSA: true tracksRegLiveness: true registers: - { id: 0, class: sreg_64 } @@ -242,7 +238,6 @@ body: | # CHECK: %1 = IMPLICIT_DEF # CHECK: S_NOP 0, implicit undef %1 name: test4 -isSSA: true tracksRegLiveness: true registers: - { id: 0, class: sreg_64 } @@ -263,7 +258,6 @@ body: | # CHECK: %1 = REG_SEQUENCE undef %0, {{[0-9]+}}, %0, {{[0-9]+}} # CHECK: S_NOP 0, implicit %1.sub1 name: test5 -isSSA: true tracksRegLiveness: true registers: - { id: 0, class: sreg_32 } @@ -290,7 +284,6 @@ body: | # CHECK: S_NOP 0, implicit %4.sub0 # CHECK: S_NOP 0, implicit undef %4.sub3 name: loop0 -isSSA: true tracksRegLiveness: true registers: - { id: 0, class: sreg_32 } @@ -344,7 +337,6 @@ body: | # CHECK: bb.2: # CHECK: S_NOP 0, implicit %6.sub3 name: loop1 -isSSA: true tracksRegLiveness: true registers: - { id: 0, class: sreg_32 } @@ -396,7 +388,6 @@ body: | # CHECK: S_NOP 0, implicit %2.sub2 # CHECK: S_NOP 0, implicit %2.sub3 name: loop2 -isSSA: true tracksRegLiveness: true registers: - { id: 0, class: sreg_32 } |
