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| author | Nirav Dave <niravd@google.com> | 2016-12-14 16:43:44 +0000 |
|---|---|---|
| committer | Nirav Dave <niravd@google.com> | 2016-12-14 16:43:44 +0000 |
| commit | f5bf03c7ef61c7e6f44ce22a5144b5e13be6e797 (patch) | |
| tree | 8bbad8c76c9b57a0cdd5914eac2c7d7e06d69de1 /llvm/test/CodeGen/AMDGPU/debugger-insert-nops.ll | |
| parent | a37860acee2d02520e32d20dffd80fe43859b419 (diff) | |
| download | bcm5719-llvm-f5bf03c7ef61c7e6f44ce22a5144b5e13be6e797.tar.gz bcm5719-llvm-f5bf03c7ef61c7e6f44ce22a5144b5e13be6e797.zip | |
Revert "In visitSTORE, always use FindBetterChain, rather than only when UseAA is enabled."
Reverting due to ARM MCJIT and MIPS LLD error.
This reverts commit r289659.
llvm-svn: 289667
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/debugger-insert-nops.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/debugger-insert-nops.ll | 24 |
1 files changed, 8 insertions, 16 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/debugger-insert-nops.ll b/llvm/test/CodeGen/AMDGPU/debugger-insert-nops.ll index 7be7d9486a4..6638f4e2582 100644 --- a/llvm/test/CodeGen/AMDGPU/debugger-insert-nops.ll +++ b/llvm/test/CodeGen/AMDGPU/debugger-insert-nops.ll @@ -1,21 +1,13 @@ -; RUN: llc -O0 -mtriple=amdgcn--amdhsa -mcpu=fiji -mattr=+amdgpu-debugger-insert-nops -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK -; RUN: llc -O0 -mtriple=amdgcn--amdhsa -mcpu=fiji -mattr=+amdgpu-debugger-insert-nops -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECKNOP +; RUN: llc -O0 -mtriple=amdgcn--amdhsa -mcpu=fiji -mattr=+amdgpu-debugger-insert-nops -verify-machineinstrs < %s | FileCheck %s -; This test expects that we have one instance for each line in some order with "s_nop 0" instances after each. - -; Check that each line appears at least once -; CHECK-DAG: test01.cl:2:3 -; CHECK-DAG: test01.cl:3:3 -; CHECK-DAG: test01.cl:4:3 +; CHECK: test01.cl:2:{{[0-9]+}} +; CHECK-NEXT: s_nop 0 +; CHECK: test01.cl:3:{{[0-9]+}} +; CHECK-NEXT: s_nop 0 -; Check that each of each of the lines consists of the line output, followed by "s_nop 0" -; CHECKNOP: test01.cl:{{[234]}}:3 -; CHECKNOP-NEXT: s_nop 0 -; CHECKNOP: test01.cl:{{[234]}}:3 -; CHECKNOP-NEXT: s_nop 0 -; CHECKNOP: test01.cl:{{[234]}}:3 -; CHECKNOP-NEXT: s_nop 0 +; CHECK: test01.cl:4:{{[0-9]+}} +; CHECK-NEXT: s_nop 0 ; CHECK: test01.cl:5:{{[0-9]+}} ; CHECK-NEXT: s_nop 0 @@ -29,7 +21,7 @@ entry: call void @llvm.dbg.declare(metadata i32 addrspace(1)** %A.addr, metadata !17, metadata !18), !dbg !19 %0 = load i32 addrspace(1)*, i32 addrspace(1)** %A.addr, align 4, !dbg !20 %arrayidx = getelementptr inbounds i32, i32 addrspace(1)* %0, i32 0, !dbg !20 - store i32 1, i32 addrspace(1)* %arrayidx, align 4, !dbg !20 + store i32 1, i32 addrspace(1)* %arrayidx, align 4, !dbg !21 %1 = load i32 addrspace(1)*, i32 addrspace(1)** %A.addr, align 4, !dbg !22 %arrayidx1 = getelementptr inbounds i32, i32 addrspace(1)* %1, i32 1, !dbg !22 store i32 2, i32 addrspace(1)* %arrayidx1, align 4, !dbg !23 |
