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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-09-08 17:19:29 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-09-08 17:19:29 +0000 |
| commit | bbb47da8a1c9303f2bd3eafbf71a522c850bae54 (patch) | |
| tree | 3c51d2943916a7fd5d0ba7930c6d86df5941e460 /llvm/test/CodeGen/AMDGPU/cvt_flr_i32_f32.ll | |
| parent | 6f605133dd72d7ae404e10e2721c2165d0965cb4 (diff) | |
| download | bcm5719-llvm-bbb47da8a1c9303f2bd3eafbf71a522c850bae54.tar.gz bcm5719-llvm-bbb47da8a1c9303f2bd3eafbf71a522c850bae54.zip | |
AMDGPU: Support commuting with immediate in src0
llvm-svn: 280970
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/cvt_flr_i32_f32.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/cvt_flr_i32_f32.ll | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/cvt_flr_i32_f32.ll b/llvm/test/CodeGen/AMDGPU/cvt_flr_i32_f32.ll index 2dd3a9f2a77..e7773c6e2a4 100644 --- a/llvm/test/CodeGen/AMDGPU/cvt_flr_i32_f32.ll +++ b/llvm/test/CodeGen/AMDGPU/cvt_flr_i32_f32.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI-SAFE -check-prefix=SI -check-prefix=FUNC %s -; RUN: llc -march=amdgcn -mcpu=SI -enable-no-nans-fp-math -verify-machineinstrs < %s | FileCheck -check-prefix=SI-NONAN -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI-SAFE -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -enable-no-nans-fp-math -verify-machineinstrs < %s | FileCheck -check-prefix=SI-NONAN -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s declare float @llvm.fabs.f32(float) #1 @@ -18,7 +18,7 @@ define void @cvt_flr_i32_f32_0(i32 addrspace(1)* %out, float %x) #0 { } ; FUNC-LABEL: {{^}}cvt_flr_i32_f32_1: -; SI: v_add_f32_e64 [[TMP:v[0-9]+]], 1.0, s{{[0-9]+}} +; SI: v_add_f32_e64 [[TMP:v[0-9]+]], s{{[0-9]+}}, 1.0 ; SI-SAFE-NOT: v_cvt_flr_i32_f32 ; SI-NONAN: v_cvt_flr_i32_f32_e32 v{{[0-9]+}}, [[TMP]] ; SI: s_endpgm |
