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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-09-09 23:32:53 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-09-09 23:32:53 +0000 |
| commit | 124384f08d4cb9b8c698951ed67fd6db79a15d15 (patch) | |
| tree | bef6b9dcd6420bcf678b0e617646e70bb06947c8 /llvm/test/CodeGen/AMDGPU/ctlz.ll | |
| parent | 8dc0e0943b9e9b864b91a50e991392db09f2dc49 (diff) | |
| download | bcm5719-llvm-124384f08d4cb9b8c698951ed67fd6db79a15d15.tar.gz bcm5719-llvm-124384f08d4cb9b8c698951ed67fd6db79a15d15.zip | |
AMDGPU: Fix immediate folding logic when shrinking instructions
If the literal is being folded into src0, it doesn't matter
if it's an SGPR because it's being replaced with the literal.
Also fixes initially selecting 32-bit versions of some instructions
which also confused commuting.
llvm-svn: 281117
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/ctlz.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/ctlz.ll | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/ctlz.ll b/llvm/test/CodeGen/AMDGPU/ctlz.ll index 2d5e9f4001d..e9d26a225e3 100644 --- a/llvm/test/CodeGen/AMDGPU/ctlz.ll +++ b/llvm/test/CodeGen/AMDGPU/ctlz.ll @@ -143,7 +143,7 @@ define void @s_ctlz_i64_trunc(i32 addrspace(1)* noalias %out, i64 %val) nounwind ; SI-DAG: v_add_i32_e32 [[ADD:v[0-9]+]], vcc, 32, [[FFBH_LO]] ; SI-DAG: v_ffbh_u32_e32 [[FFBH_HI:v[0-9]+]], v[[HI]] ; SI-DAG: v_cndmask_b32_e64 v[[CTLZ:[0-9]+]], [[FFBH_HI]], [[ADD]], [[CMPHI]] -; SI-DAG: v_or_b32_e32 [[OR:v[0-9]+]], v[[LO]], v[[HI]] +; SI-DAG: v_or_b32_e32 [[OR:v[0-9]+]], v[[HI]], v[[LO]] ; SI-DAG: v_cmp_eq_i32_e32 vcc, 0, [[OR]] ; SI-DAG: v_cndmask_b32_e64 v[[CLTZ_LO:[0-9]+]], v[[CTLZ:[0-9]+]], 64, vcc ; SI: {{buffer|flat}}_store_dwordx2 {{.*}}v{{\[}}[[CLTZ_LO]]:[[CTLZ_HI]]{{\]}} |
