diff options
| author | Alexander Timofeev <Alexander.Timofeev@amd.com> | 2019-10-14 12:01:10 +0000 |
|---|---|---|
| committer | Alexander Timofeev <Alexander.Timofeev@amd.com> | 2019-10-14 12:01:10 +0000 |
| commit | c4d256a59049d4b2f21da83f43b9caba2427885e (patch) | |
| tree | 933fb661becfcd18c242cb6dee0829d0b2793a92 /llvm/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll | |
| parent | d34822ad4c42867ccdd24f8e50d57b37a7969680 (diff) | |
| download | bcm5719-llvm-c4d256a59049d4b2f21da83f43b9caba2427885e.tar.gz bcm5719-llvm-c4d256a59049d4b2f21da83f43b9caba2427885e.zip | |
[AMDGPU] Come back patch for the 'Assign register class for cross block values according to the divergence.'
Detailed description:
After https://reviews.llvm.org/D59990 submit several issues were discovered.
Changes in common code were preserved but AMDGPU specific part was reverted to keep the backend working correctly.
Discovered issues were addressed in the following commits:
https://reviews.llvm.org/D67662
https://reviews.llvm.org/D67101
https://reviews.llvm.org/D63953
https://reviews.llvm.org/D63731
This change brings back AMDGPU specific changes.
Reviewed by: rampitec, arsenm
Differential Revision: https://reviews.llvm.org/D68635
llvm-svn: 374767
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll b/llvm/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll index 41ecdd403d7..15e807a3e02 100644 --- a/llvm/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll +++ b/llvm/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll @@ -89,7 +89,7 @@ endif: } ; GCN-LABEL: {{^}}divergent_loop: -; VGPR: workitem_private_segment_byte_size = 16{{$}} +; VGPR: workitem_private_segment_byte_size = 12{{$}} ; GCN: {{^}}; %bb.0: @@ -123,10 +123,9 @@ endif: ; GCN: [[LOOP:BB[0-9]+_[0-9]+]]: ; GCN: buffer_load_dword v[[VAL_LOOP_RELOAD:[0-9]+]], off, s[0:3], s7 offset:[[LOAD0_OFFSET]] ; 4-byte Folded Reload ; GCN: v_subrev_i32_e32 [[VAL_LOOP:v[0-9]+]], vcc, v{{[0-9]+}}, v[[VAL_LOOP_RELOAD]] -; GCN: v_cmp_ne_u32_e32 vcc, -; GCN: s_and_b64 vcc, exec, vcc +; GCN: s_cmp_lg_u32 ; GCN: buffer_store_dword [[VAL_LOOP]], off, s[0:3], s7 offset:[[VAL_SUB_OFFSET:[0-9]+]] ; 4-byte Folded Spill -; GCN-NEXT: s_cbranch_vccnz [[LOOP]] +; GCN-NEXT: s_cbranch_scc1 [[LOOP]] ; GCN: [[END]]: |
