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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2018-03-19 14:07:15 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2018-03-19 14:07:15 +0000 |
| commit | 69932e4d692f20615935db0d48f45b21a89cae23 (patch) | |
| tree | fb8a00b0e01ac285170c95f7bc35eae639489f4f /llvm/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll | |
| parent | 1af12b587bee97e6a4926e842b181643abce6504 (diff) | |
| download | bcm5719-llvm-69932e4d692f20615935db0d48f45b21a89cae23.tar.gz bcm5719-llvm-69932e4d692f20615935db0d48f45b21a89cae23.zip | |
AMDGPU: Don't leave dead illegal VGPR->SGPR copies
Normally DCE kills these, but at -O0 these get left behind
leaving suspicious looking illegal copies.
Replace with IMPLICIT_DEF to avoid iterator issues.
llvm-svn: 327842
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll b/llvm/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll index 071bcbcf81b..c51b8e0efa0 100644 --- a/llvm/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll +++ b/llvm/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll @@ -41,16 +41,17 @@ ; GCN: {{^}}BB{{[0-9]+}}_1: ; %if ; GCN: s_mov_b32 m0, -1 ; GCN: ds_read_b32 [[LOAD1:v[0-9]+]] -; GCN: s_waitcnt lgkmcnt(0) ; GCN: buffer_load_dword [[RELOAD_LOAD0:v[0-9]+]], off, s[0:3], s7 offset:[[LOAD0_OFFSET]] ; 4-byte Folded Reload +; GCN: s_waitcnt vmcnt(0) lgkmcnt(0) + ; Spill val register ; GCN: v_add_i32_e32 [[VAL:v[0-9]+]], vcc, [[LOAD1]], [[RELOAD_LOAD0]] ; GCN: buffer_store_dword [[VAL]], off, s[0:3], s7 offset:[[VAL_OFFSET:[0-9]+]] ; 4-byte Folded Spill ; VMEM: [[ENDIF]]: + ; Reload and restore exec mask -; VGPR: s_waitcnt lgkmcnt(0) ; VGPR: v_readlane_b32 s[[S_RELOAD_SAVEEXEC_LO:[0-9]+]], [[SPILL_VGPR]], [[SAVEEXEC_LO_LANE]] ; VGPR: v_readlane_b32 s[[S_RELOAD_SAVEEXEC_HI:[0-9]+]], [[SPILL_VGPR]], [[SAVEEXEC_HI_LANE]] |
