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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-08-27 19:05:33 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-08-27 19:05:33 +0000 |
| commit | 2910184936e31cd69b09bad0c87161da384f57df (patch) | |
| tree | 4119cf5e0c989ed47b2e62ad9263f870d5e46cdb /llvm/test/CodeGen/AMDGPU/computeNumSignBits-mul.ll | |
| parent | 2797474dbb96d39c286b1d4e6875e2ee91876f47 (diff) | |
| download | bcm5719-llvm-2910184936e31cd69b09bad0c87161da384f57df.tar.gz bcm5719-llvm-2910184936e31cd69b09bad0c87161da384f57df.zip | |
DAG: computeNumSignBits for MUL
Copied directly from the IR version.
Most of the testcases I've added for this are somewhat problematic
because they really end up testing the yet to be implemented version
for MUL_I24/MUL_U24.
llvm-svn: 370099
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/computeNumSignBits-mul.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/computeNumSignBits-mul.ll | 19 |
1 files changed, 5 insertions, 14 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/computeNumSignBits-mul.ll b/llvm/test/CodeGen/AMDGPU/computeNumSignBits-mul.ll index 54ab5d165be..125f76ae10e 100644 --- a/llvm/test/CodeGen/AMDGPU/computeNumSignBits-mul.ll +++ b/llvm/test/CodeGen/AMDGPU/computeNumSignBits-mul.ll @@ -7,7 +7,7 @@ define i16 @num_sign_bits_mul_i48_0(i8 %X, i8 %Y, i8 %Z, i8 %W) { ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: v_mul_i32_i24_sdwa v0, sext(v0), sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0 ; GFX9-NEXT: v_mul_i32_i24_sdwa v1, sext(v2), sext(v3) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0 -; GFX9-NEXT: v_mul_lo_u32 v0, v0, v1 +; GFX9-NEXT: v_mul_i32_i24_e32 v0, v0, v1 ; GFX9-NEXT: s_setpc_b64 s[30:31] %A = sext i8 %X to i48 %B = sext i8 %Y to i48 @@ -24,19 +24,10 @@ define i16 @num_sign_bits_mul_i48_1(i8 %X, i8 %Y, i8 %Z, i8 %W) { ; GFX9-LABEL: num_sign_bits_mul_i48_1: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_bfe_i32 v1, v1, 0, 8 -; GFX9-NEXT: v_bfe_i32 v0, v0, 0, 8 -; GFX9-NEXT: v_mul_hi_i32_i24_e32 v4, v0, v1 -; GFX9-NEXT: v_mul_i32_i24_e32 v0, v0, v1 -; GFX9-NEXT: v_bfe_i32 v1, v3, 0, 8 -; GFX9-NEXT: v_bfe_i32 v2, v2, 0, 8 -; GFX9-NEXT: v_mul_hi_i32_i24_e32 v3, v2, v1 -; GFX9-NEXT: v_mul_i32_i24_e32 v1, v2, v1 -; GFX9-NEXT: v_mul_lo_u32 v2, v4, v1 -; GFX9-NEXT: v_mul_lo_u32 v3, v0, v3 -; GFX9-NEXT: v_mul_hi_u32 v4, v0, v1 -; GFX9-NEXT: v_mul_lo_u32 v0, v0, v1 -; GFX9-NEXT: v_add3_u32 v1, v4, v3, v2 +; GFX9-NEXT: v_mul_i32_i24_sdwa v0, sext(v0), sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0 +; GFX9-NEXT: v_mul_i32_i24_sdwa v2, sext(v2), sext(v3) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0 +; GFX9-NEXT: v_mul_hi_i32_i24_e32 v1, v0, v2 +; GFX9-NEXT: v_mul_i32_i24_e32 v0, v0, v2 ; GFX9-NEXT: v_lshrrev_b64 v[0:1], 24, v[0:1] ; GFX9-NEXT: s_setpc_b64 s[30:31] %A = sext i8 %X to i48 |
