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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-03-27 16:58:22 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-03-27 16:58:22 +0000 |
| commit | a42b7247d36a43d5c5b58c99aafce9ad6d1fe796 (patch) | |
| tree | 2109d5e17a06482605389fb12126c80d4189d6df /llvm/test/CodeGen/AMDGPU/coalescing-with-subregs-in-loop-bug.mir | |
| parent | f5f8d27d39126a4aa893fb32d7e5952cd8ca504b (diff) | |
| download | bcm5719-llvm-a42b7247d36a43d5c5b58c99aafce9ad6d1fe796.tar.gz bcm5719-llvm-a42b7247d36a43d5c5b58c99aafce9ad6d1fe796.zip | |
AMDGPU: Fix missing scc implicit def on s_andn2_b64_term
Introduce new helper class to copy properties directly from the base
instruction.
llvm-svn: 357089
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/coalescing-with-subregs-in-loop-bug.mir')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/coalescing-with-subregs-in-loop-bug.mir | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/coalescing-with-subregs-in-loop-bug.mir b/llvm/test/CodeGen/AMDGPU/coalescing-with-subregs-in-loop-bug.mir index 37a0eb40b55..cd4a851bc3e 100644 --- a/llvm/test/CodeGen/AMDGPU/coalescing-with-subregs-in-loop-bug.mir +++ b/llvm/test/CodeGen/AMDGPU/coalescing-with-subregs-in-loop-bug.mir @@ -83,7 +83,7 @@ body: | %43:sreg_64 = COPY %1 %44:vreg_128 = COPY %35 %45:vreg_128 = COPY killed %30 - $exec = S_ANDN2_B64_term $exec, %1 + $exec = S_ANDN2_B64_term $exec, %1, implicit-def $scc S_CBRANCH_EXECNZ %bb.1, implicit $exec S_BRANCH %bb.2 |
