AMDGPU: Convert image intrinsic uses in tests

llvm-svn: 298386

1 files changed, 10 insertions, 18 deletions

diff --git a/llvm/test/CodeGen/AMDGPU/coalescer-subrange-crash.ll b/llvm/test/CodeGen/AMDGPU/coalescer-subrange-crash.ll
index 24d0406b4c6..ef1b3d25f88 100644
--- a/llvm/test/CodeGen/AMDGPU/coalescer-subrange-crash.ll
+++ b/llvm/test/CodeGen/AMDGPU/coalescer-subrange-crash.ll
@@ -36,7 +36,8 @@ main_body:
   %tmp31 = insertelement <16 x i32> %tmp30, i32 undef, i32 6
   %tmp32 = insertelement <16 x i32> %tmp31, i32 undef, i32 7
   %tmp33 = insertelement <16 x i32> %tmp32, i32 undef, i32 8
-  %tmp34 = call <4 x float> @llvm.SI.image.sample.c.d.o.v16i32(<16 x i32> %tmp33, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
+  %tmp33.bc = bitcast <16 x i32> %tmp33 to <16 x float>
+  %tmp34 = call <4 x float> @llvm.amdgcn.image.sample.c.d.o.v4f32.v16f32.v8i32(<16 x float> %tmp33.bc, <8 x i32> undef, <4 x i32> undef, i32 15, i1 false, i1 false, i1 false, i1 false, i1 true)
   %tmp35 = extractelement <4 x float> %tmp34, i32 0
   %tmp36 = bitcast float %tmp24 to i32
   %tmp37 = insertelement <16 x i32> <i32 212739, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>, i32 %tmp36, i32 1
@@ -47,7 +48,8 @@ main_body:
   %tmp42 = insertelement <16 x i32> %tmp41, i32 undef, i32 6
   %tmp43 = insertelement <16 x i32> %tmp42, i32 undef, i32 7
   %tmp44 = insertelement <16 x i32> %tmp43, i32 undef, i32 8
-  %tmp45 = call <4 x float> @llvm.SI.image.sample.c.d.o.v16i32(<16 x i32> %tmp44, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
+  %tmp44.bc = bitcast <16 x i32> %tmp44 to <16 x float>
+  %tmp45 = call <4 x float> @llvm.amdgcn.image.sample.c.d.o.v4f32.v16f32.v8i32(<16 x float> %tmp44.bc, <8 x i32> undef, <4 x i32> undef, i32 15, i1 false, i1 false, i1 false, i1 false, i1 true)
   %tmp46 = extractelement <4 x float> %tmp45, i32 0
   %tmp47 = fmul float %tmp35, %tmp46
   %tmp48 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> undef, float %tmp47, 14
@@ -55,20 +57,10 @@ main_body:
   ret <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %tmp49
 }
 
-; Function Attrs: nounwind readnone
-declare float @llvm.SI.load.const(<16 x i8>, i32) #0
+declare float @llvm.amdgcn.interp.p1(float, i32, i32, i32) #1
+declare float @llvm.amdgcn.interp.p2(float, float, i32, i32, i32) #1
+declare <4 x float> @llvm.amdgcn.image.sample.c.d.o.v4f32.v16f32.v8i32(<16 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #2
 
-; Function Attrs: nounwind readnone
-declare <4 x float> @llvm.SI.image.sample.c.d.o.v16i32(<16 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #0
-
-; Function Attrs: nounwind readnone
-declare float @llvm.amdgcn.interp.p1(float, i32, i32, i32) #0
-
-; Function Attrs: nounwind readnone
-declare float @llvm.amdgcn.interp.p2(float, float, i32, i32, i32) #0
-
-; Function Attrs: nounwind readnone
-declare float @llvm.amdgcn.interp.mov(i32, i32, i32, i32) #0
-
-attributes #0 = { nounwind readnone }
-attributes #1 = { nounwind }
+attributes #0 = { nounwind }
+attributes #1 = { nounwind readnone }
+attributes #2 = { nounwind readonly }