diff options
| author | Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> | 2017-06-28 02:52:39 +0000 |
|---|---|---|
| committer | Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> | 2017-06-28 02:52:39 +0000 |
| commit | d445455643900416388b5819ebbdfc39329ab8cc (patch) | |
| tree | 8c2c87369ff90e34789b8db8390ad732a6fee292 /llvm/test/CodeGen/AMDGPU/cgp-bitfield-extract.ll | |
| parent | eb40733bf07e523ff898cbad942c9dbbc5beaca2 (diff) | |
| download | bcm5719-llvm-d445455643900416388b5819ebbdfc39329ab8cc.tar.gz bcm5719-llvm-d445455643900416388b5819ebbdfc39329ab8cc.zip | |
[AMDGPU] Add pattern for v_alignbit_b32 with immediate
If immediate in shift is less than 32 we can use alignbit too.
Differential Revision: https://reviews.llvm.org/D34729
llvm-svn: 306500
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/cgp-bitfield-extract.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/cgp-bitfield-extract.ll | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/cgp-bitfield-extract.ll b/llvm/test/CodeGen/AMDGPU/cgp-bitfield-extract.ll index 53adf09026e..04ad3bcccd3 100644 --- a/llvm/test/CodeGen/AMDGPU/cgp-bitfield-extract.ll +++ b/llvm/test/CodeGen/AMDGPU/cgp-bitfield-extract.ll @@ -176,14 +176,13 @@ ret: ; OPT: ret ; GCN-LABEL: {{^}}sink_ubfe_i64_span_midpoint: -; GCN: s_cbranch_scc1 BB3_2 -; GCN: s_lshr_b64 s{{\[}}[[LO:[0-9]+]]:{{[0-9]+}}], s{{\[[0-9]+:[0-9]+\]}}, 30 -; GCN: s_and_b32 s{{[0-9]+}}, s[[LO]], 0xff +; GCN: v_alignbit_b32 v[[LO:[0-9]+]], s{{[0-9]+}}, v{{[0-9]+}}, 30 +; GCN: s_cbranch_scc1 BB3_2 +; GCN: v_and_b32_e32 v{{[0-9]+}}, 0xff, v[[LO]] ; GCN: BB3_2: -; GCN: s_lshr_b64 s{{\[}}[[LO:[0-9]+]]:{{[0-9]+}}], s{{\[[0-9]+:[0-9]+\]}}, 30 -; GCN: s_and_b32 s{{[0-9]+}}, s[[LO]], 0x7f +; GCN: v_and_b32_e32 v{{[0-9]+}}, 0x7f, v[[LO]] ; GCN: BB3_3: ; GCN: buffer_store_dwordx2 |
