diff options
| author | Tom Stellard <thomas.stellard@amd.com> | 2016-03-30 16:35:09 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2016-03-30 16:35:09 +0000 |
| commit | 0bc954e3bc474383f87ab9e55ab1aa5ae996f9c0 (patch) | |
| tree | d428795eaee9170ce8fc563a9634e2568806147e /llvm/test/CodeGen/AMDGPU/captured-frame-index.ll | |
| parent | f76123386a7867ff5fa63a55841668ac098e201e (diff) | |
| download | bcm5719-llvm-0bc954e3bc474383f87ab9e55ab1aa5ae996f9c0.tar.gz bcm5719-llvm-0bc954e3bc474383f87ab9e55ab1aa5ae996f9c0.zip | |
AMDGPU/SI: Enable lanemask tracking in misched
Summary:
This results in higher register usage, but should make it easier for
the compiler to hide latency.
This pass is a prerequisite for some more scheduler improvements, and I
think the increase register usage with this patch is acceptable, because
when combined with the scheduler improvements, the total register usage
will decrease.
shader-db stats:
2382 shaders in 478 tests
Totals:
SGPRS: 48672 -> 49088 (0.85 %)
VGPRS: 34148 -> 34847 (2.05 %)
Code Size: 1285816 -> 1289128 (0.26 %) bytes
LDS: 28 -> 28 (0.00 %) blocks
Scratch: 492544 -> 573440 (16.42 %) bytes per wave
Max Waves: 6856 -> 6846 (-0.15 %)
Wait states: 0 -> 0 (0.00 %)
Depends on D18451
Reviewers: nhaehnle, arsenm
Subscribers: arsenm, llvm-commits
Differential Revision: http://reviews.llvm.org/D18452
llvm-svn: 264876
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/captured-frame-index.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/captured-frame-index.ll | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/captured-frame-index.ll b/llvm/test/CodeGen/AMDGPU/captured-frame-index.ll index 6b70c931feb..7e2b98e7c5a 100644 --- a/llvm/test/CodeGen/AMDGPU/captured-frame-index.ll +++ b/llvm/test/CodeGen/AMDGPU/captured-frame-index.ll @@ -2,12 +2,10 @@ ; GCN-LABEL: {{^}}stored_fi_to_lds: ; GCN: s_load_dword [[LDSPTR:s[0-9]+]] -; GCN: v_mov_b32_e32 [[ZERO0:v[0-9]+]], 0{{$}} ; GCN: v_mov_b32_e32 [[ZERO1:v[0-9]+]], 0{{$}} ; GCN: buffer_store_dword v{{[0-9]+}}, [[ZERO1]] - +; GCN: v_mov_b32_e32 [[ZERO0:v[0-9]+]], 0{{$}} ; GCN: v_mov_b32_e32 [[VLDSPTR:v[0-9]+]], [[LDSPTR]] - ; GCN: ds_write_b32 [[VLDSPTR]], [[ZERO0]] define void @stored_fi_to_lds(float* addrspace(3)* %ptr) #0 { %tmp = alloca float @@ -19,7 +17,6 @@ define void @stored_fi_to_lds(float* addrspace(3)* %ptr) #0 { ; Offset is applied ; GCN-LABEL: {{^}}stored_fi_to_lds_2_small_objects: ; GCN: s_load_dword [[LDSPTR:s[0-9]+]] -; GCN: v_mov_b32_e32 [[ZERO0:v[0-9]+]], 0{{$}} ; GCN: v_mov_b32_e32 [[ZERO1:v[0-9]+]], 0{{$}} ; GCN: buffer_store_dword v{{[0-9]+}}, [[ZERO1]] @@ -27,6 +24,7 @@ define void @stored_fi_to_lds(float* addrspace(3)* %ptr) #0 { ; GCN: buffer_store_dword v{{[0-9]+}}, [[FI1]] +; GCN-DAG: v_mov_b32_e32 [[ZERO0:v[0-9]+]], 0{{$}} ; GCN-DAG: v_mov_b32_e32 [[VLDSPTR:v[0-9]+]], [[LDSPTR]] ; GCN: ds_write_b32 [[VLDSPTR]], [[ZERO0]] |
