[AMDGPU] Prepare for introduction of v3 and v5 MVTs

AMDGPU would like to have MVTs for v3i32, v3f32, v5i32, v5f32. This
commit does not add them, but makes preparatory changes:

* Fixed assumptions of power-of-2 vector type in kernel arg handling,
  and added v5 kernel arg tests and v3/v5 shader arg tests.

* Added v5 tests for cost analysis.

* Added vec3/vec5 arg test cases.

Some of this patch is from Matt Arsenault, also of AMD.

Differential Revision: https://reviews.llvm.org/D58928

Change-Id: I7279d6b4841464d2080eb255ef3c589e268eabcd
llvm-svn: 356342

1 files changed, 90 insertions, 0 deletions

diff --git a/llvm/test/CodeGen/AMDGPU/calling-conventions.ll b/llvm/test/CodeGen/AMDGPU/calling-conventions.ll
index 6dc6b8c2daf..1409f843cda 100644
--- a/llvm/test/CodeGen/AMDGPU/calling-conventions.ll
+++ b/llvm/test/CodeGen/AMDGPU/calling-conventions.ll
@@ -200,4 +200,94 @@ define amdgpu_ps void @ps_mesa_inreg_v2i16(<2 x i16> inreg %arg0) {
   ret void
 }
 
+; GCN-LABEL: {{^}}ps_mesa_inreg_v3i32:
+; GCN-DAG: s_add_i32 s0, s0, 1
+; GCN-DAG: s_add_i32 s{{[0-9]*}}, s1, 2
+; GCN-DAG: s_add_i32 s{{[0-9]*}}, s2, 3
+define amdgpu_ps void @ps_mesa_inreg_v3i32(<3 x i32> inreg %arg0) {
+  %add = add <3 x i32> %arg0, <i32 1, i32 2, i32 3>
+  store <3 x i32> %add, <3 x i32> addrspace(1)* undef
+  ret void
+}
+
+; GCN-LABEL: {{^}}ps_mesa_inreg_v3f32:
+; GCN-DAG: v_add_f32{{.*}}, s0, 1.0
+; GCN-DAG: v_add_f32{{.*}}, s1, 2.0
+; GCN-DAG: v_add_f32{{.*}}, s2, 4.0
+define amdgpu_ps void @ps_mesa_inreg_v3f32(<3 x float> inreg %arg0) {
+  %add = fadd <3 x float> %arg0, <float 1.0, float 2.0, float 4.0>
+  store <3 x float> %add, <3 x float> addrspace(1)* undef
+  ret void
+}
+
+; GCN-LABEL: {{^}}ps_mesa_inreg_v5i32:
+; GCN-DAG: s_add_i32 s0, s0, 1
+; GCN-DAG: s_add_i32 s{{[0-9]*}}, s1, 2
+; GCN-DAG: s_add_i32 s{{[0-9]*}}, s2, 3
+; GCN-DAG: s_add_i32 s{{[0-9]*}}, s3, 4
+; GCN-DAG: s_add_i32 s{{[0-9]*}}, s4, 5
+define amdgpu_ps void @ps_mesa_inreg_v5i32(<5 x i32> inreg %arg0) {
+  %add = add <5 x i32> %arg0, <i32 1, i32 2, i32 3, i32 4, i32 5>
+  store <5 x i32> %add, <5 x i32> addrspace(1)* undef
+  ret void
+}
+
+; GCN-LABEL: {{^}}ps_mesa_inreg_v5f32:
+; GCN-DAG: v_add_f32{{.*}}, s0, 1.0
+; GCN-DAG: v_add_f32{{.*}}, s1, 2.0
+; GCN-DAG: v_add_f32{{.*}}, s2, 4.0
+; GCN-DAG: v_add_f32{{.*}}, s3, -1.0
+; GCN-DAG: v_add_f32{{.*}}, s4, 0.5
+define amdgpu_ps void @ps_mesa_inreg_v5f32(<5 x float> inreg %arg0) {
+  %add = fadd <5 x float> %arg0, <float 1.0, float 2.0, float 4.0, float -1.0, float 0.5>
+  store <5 x float> %add, <5 x float> addrspace(1)* undef
+  ret void
+}
+
+; GCN-LABEL: {{^}}ps_mesa_v3i32:
+; GCN-DAG: v_add_{{.*}}, 1, v0
+; GCN-DAG: v_add_{{.*}}, 2, v1
+; GCN-DAG: v_add_{{.*}}, 3, v2
+define amdgpu_ps void @ps_mesa_v3i32(<3 x i32> %arg0) {
+  %add = add <3 x i32> %arg0, <i32 1, i32 2, i32 3>
+  store <3 x i32> %add, <3 x i32> addrspace(1)* undef
+  ret void
+}
+
+; GCN-LABEL: {{^}}ps_mesa_v3f32:
+; GCN-DAG: v_add_{{.*}}, 1.0, v0
+; GCN-DAG: v_add_{{.*}}, 2.0, v1
+; GCN-DAG: v_add_{{.*}}, 4.0, v2
+define amdgpu_ps void @ps_mesa_v3f32(<3 x float> %arg0) {
+  %add = fadd <3 x float> %arg0, <float 1.0, float 2.0, float 4.0>
+  store <3 x float> %add, <3 x float> addrspace(1)* undef
+  ret void
+}
+
+; GCN-LABEL: {{^}}ps_mesa_v5i32:
+; GCN-DAG: v_add_{{.*}}, 1, v0
+; GCN-DAG: v_add_{{.*}}, 2, v1
+; GCN-DAG: v_add_{{.*}}, 3, v2
+; GCN-DAG: v_add_{{.*}}, 4, v3
+; GCN-DAG: v_add_{{.*}}, 5, v4
+define amdgpu_ps void @ps_mesa_v5i32(<5 x i32> %arg0) {
+  %add = add <5 x i32> %arg0, <i32 1, i32 2, i32 3, i32 4, i32 5>
+  store <5 x i32> %add, <5 x i32> addrspace(1)* undef
+  ret void
+}
+
+; GCN-LABEL: {{^}}ps_mesa_v5f32:
+; GCN-DAG: v_add_f32{{.*}}, 1.0, v0
+; GCN-DAG: v_add_f32{{.*}}, 2.0, v1
+; GCN-DAG: v_add_f32{{.*}}, 4.0, v2
+; GCN-DAG: v_add_f32{{.*}}, -1.0, v3
+; GCN-DAG: v_add_f32{{.*}}, 0.5, v4
+define amdgpu_ps void @ps_mesa_v5f32(<5 x float> %arg0) {
+  %add = fadd <5 x float> %arg0, <float 1.0, float 2.0, float 4.0, float -1.0, float 0.5>
+  store <5 x float> %add, <5 x float> addrspace(1)* undef
+  ret void
+}
+
+
+
 attributes #0 = { nounwind noinline }