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| author | Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> | 2017-07-26 21:29:15 +0000 |
|---|---|---|
| committer | Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> | 2017-07-26 21:29:15 +0000 |
| commit | 3197eb69812f9ff1c0ef4b2a7b894397dec3de24 (patch) | |
| tree | 9eb5e70f569cbb3569bcf3c65be5a9bc02fa5265 /llvm/test/CodeGen/AMDGPU/branch-condition-and.ll | |
| parent | b3ed4bcb8f1b0a9343d47628ae98127ca33575d1 (diff) | |
| download | bcm5719-llvm-3197eb69812f9ff1c0ef4b2a7b894397dec3de24.tar.gz bcm5719-llvm-3197eb69812f9ff1c0ef4b2a7b894397dec3de24.zip | |
[AMDGPU] Optimize SI_IF lowering for simple if regions
Currently SI_IF results in a s_and_saveexec_b64 followed by s_xor_b64.
The xor is used to extract only the changed bits. In case of a simple
if region where the only use of that value is in the SI_END_CF to
restore the old exec mask, we can omit the xor and perform an or of
the exec mask with the original exec value saved by the
s_and_saveexec_b64.
Differential Revision: https://reviews.llvm.org/D35861
llvm-svn: 309185
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/branch-condition-and.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/branch-condition-and.ll | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/branch-condition-and.ll b/llvm/test/CodeGen/AMDGPU/branch-condition-and.ll index 662ea37a2b9..51b91ee286f 100644 --- a/llvm/test/CodeGen/AMDGPU/branch-condition-and.ll +++ b/llvm/test/CodeGen/AMDGPU/branch-condition-and.ll @@ -14,7 +14,6 @@ ; GCN-DAG: v_cmp_lt_f32_e32 vcc, ; GCN: s_and_b64 [[AND:s\[[0-9]+:[0-9]+\]]], vcc, [[OTHERCC]] ; GCN: s_and_saveexec_b64 [[SAVED:s\[[0-9]+:[0-9]+\]]], [[AND]] -; GCN: s_xor_b64 {{s\[[0-9]+:[0-9]+\]}}, exec, [[SAVED]] ; GCN: ; mask branch [[BB5:BB[0-9]+_[0-9]+]] ; GCN-NEXT: BB{{[0-9]+_[0-9]+}}: ; %bb4 |
