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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-12-06 01:02:51 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-12-06 01:02:51 +0000 |
| commit | ad55ee58691b58f3ac36e688fc90808d5cf71e7f (patch) | |
| tree | 712b24af2cc28eb96613647ee32d130ba02f8d03 /llvm/test/CodeGen/AMDGPU/br_cc.f16.ll | |
| parent | 9642b36e91c28b888db018ebec8998b5bee33338 (diff) | |
| download | bcm5719-llvm-ad55ee58691b58f3ac36e688fc90808d5cf71e7f.tar.gz bcm5719-llvm-ad55ee58691b58f3ac36e688fc90808d5cf71e7f.zip | |
AMDGPU: Don't required structured CFG
The structured CFG is just an aid to inserting exec
mask modification instructions, once that is done
we don't really need it anymore. We also
do not analyze blocks with terminators that
modify exec, so this should only be impacting
true branches.
llvm-svn: 288744
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/br_cc.f16.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/br_cc.f16.ll | 25 |
1 files changed, 13 insertions, 12 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/br_cc.f16.ll b/llvm/test/CodeGen/AMDGPU/br_cc.f16.ll index 6cf3fdad3e3..970260412c4 100644 --- a/llvm/test/CodeGen/AMDGPU/br_cc.f16.ll +++ b/llvm/test/CodeGen/AMDGPU/br_cc.f16.ll @@ -12,9 +12,10 @@ ; GCN: s_cbranch_vccnz ; GCN: one{{$}} -; SI: v_cvt_f16_f32_e32 v[[A_F16:[0-9]+]], v[[A_F32]] -; GCN: buffer_store_short v[[A_F16]] -; GCN: s_endpgm +; SI: v_cvt_f16_f32_e32 v[[A_F16:[0-9]+]], v[[A_F32]] +; SI: s_branch +; VI: buffer_store_short +; VI: s_endpgm ; GCN: two{{$}} ; SI: v_cvt_f16_f32_e32 v[[B_F16:[0-9]+]], v[[B_F32]] @@ -47,17 +48,19 @@ two: ; SI: v_cvt_f32_f16_e32 v[[B_F32:[0-9]+]], v[[B_F16]] ; SI: v_cmp_ngt_f32_e32 vcc, v[[B_F32]], v[[A_F32]] ; VI: v_cmp_nle_f16_e32 vcc, v[[A_F16]], v[[B_F16]] -; GCN: s_cbranch_vccnz +; SI: s_cbranch_vccz +; VI: s_cbranch_vccnz -; GCN: one{{$}} -; VI: v_mov_b32_e32 v[[A_F16:[0-9]+]], 0x3800{{$}} -; GCN: buffer_store_short v[[A_F16]] -; GCN: s_endpgm +; VI: one{{$}} +; VI: v_mov_b32_e32 v[[A_F16:[0-9]+]], 0x380{{0|1}}{{$}} ; GCN: two{{$}} ; SI: v_cvt_f16_f32_e32 v[[B_F16:[0-9]+]], v[[B_F32]] -; GCN: buffer_store_short v[[B_F16]] -; GCN: s_endpgm + +; SI: one{{$}} +; SI: buffer_store_short v[[A_F16]] +; SI: s_endpgm + define void @br_cc_f16_imm_a( half addrspace(1)* %r, half addrspace(1)* %b) { @@ -87,8 +90,6 @@ two: ; GCN: one{{$}} ; SI: v_cvt_f16_f32_e32 v[[A_F16:[0-9]+]], v[[A_F32]] -; GCN: buffer_store_short v[[A_F16]] -; GCN: s_endpgm ; GCN: two{{$}} ; VI: v_mov_b32_e32 v[[B_F16:[0-9]+]], 0x3800{{$}} |
