diff options
author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-11-01 23:14:20 +0000 |
---|---|---|
committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-11-01 23:14:20 +0000 |
commit | 663ab8c1190c78a534c4bce1d6c8093537e06a72 (patch) | |
tree | 8f3f737865ad46fb80dd9d7249f0ede72fda6348 /llvm/test/CodeGen/AMDGPU/bitreverse-inline-immediates.ll | |
parent | cfadbd947808e81f760f344477121a7028ff1edc (diff) | |
download | bcm5719-llvm-663ab8c1190c78a534c4bce1d6c8093537e06a72.tar.gz bcm5719-llvm-663ab8c1190c78a534c4bce1d6c8093537e06a72.zip |
AMDGPU: Use brev for materializing SGPR constants
This is already done with VGPR immediates and saves 4 bytes.
llvm-svn: 285765
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/bitreverse-inline-immediates.ll')
-rw-r--r-- | llvm/test/CodeGen/AMDGPU/bitreverse-inline-immediates.ll | 63 |
1 files changed, 63 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/bitreverse-inline-immediates.ll b/llvm/test/CodeGen/AMDGPU/bitreverse-inline-immediates.ll index 150e3430a5e..f7dc1a9d37e 100644 --- a/llvm/test/CodeGen/AMDGPU/bitreverse-inline-immediates.ll +++ b/llvm/test/CodeGen/AMDGPU/bitreverse-inline-immediates.ll @@ -156,3 +156,66 @@ define void @materialize_rev_1.0_i64(i64 addrspace(1)* %out) { store i64 508, i64 addrspace(1)* %out ret void } + +; GCN-LABEL: {{^}}s_materialize_0_i32: +; GCN: s_mov_b32 s{{[0-9]+}}, 0{{$}} +define void @s_materialize_0_i32() { + call void asm sideeffect "; use $0", "s"(i32 0) + ret void +} + +; GCN-LABEL: {{^}}s_materialize_1_i32: +; GCN: s_mov_b32 s{{[0-9]+}}, 1{{$}} +define void @s_materialize_1_i32() { + call void asm sideeffect "; use $0", "s"(i32 1) + ret void +} + +; GCN-LABEL: {{^}}s_materialize_neg1_i32: +; GCN: s_mov_b32 s{{[0-9]+}}, -1{{$}} +define void @s_materialize_neg1_i32() { + call void asm sideeffect "; use $0", "s"(i32 -1) + ret void +} + +; GCN-LABEL: {{^}}s_materialize_signbit_i32: +; GCN: s_brev_b32 s{{[0-9]+}}, 1{{$}} +define void @s_materialize_signbit_i32() { + call void asm sideeffect "; use $0", "s"(i32 -2147483648) + ret void +} + +; GCN-LABEL: {{^}}s_materialize_rev_64_i32: +; GCN: s_brev_b32 s{{[0-9]+}}, 64{{$}} +define void @s_materialize_rev_64_i32() { + call void asm sideeffect "; use $0", "s"(i32 33554432) + ret void +} + +; GCN-LABEL: {{^}}s_materialize_rev_65_i32: +; GCN: s_mov_b32 s{{[0-9]+}}, 0x82000000{{$}} +define void @s_materialize_rev_65_i32() { + call void asm sideeffect "; use $0", "s"(i32 -2113929216) + ret void +} + +; GCN-LABEL: {{^}}s_materialize_rev_neg16_i32: +; GCN: s_brev_b32 s{{[0-9]+}}, -16{{$}} +define void @s_materialize_rev_neg16_i32() { + call void asm sideeffect "; use $0", "s"(i32 268435455) + ret void +} + +; GCN-LABEL: {{^}}s_materialize_rev_neg17_i32: +; GCN: s_mov_b32 s{{[0-9]+}}, 0xf7ffffff{{$}} +define void @s_materialize_rev_neg17_i32() { + call void asm sideeffect "; use $0", "s"(i32 -134217729) + ret void +} + +; GCN-LABEL: {{^}}s_materialize_rev_1.0_i32: +; GCN: s_movk_i32 s{{[0-9]+}}, 0x1fc{{$}} +define void @s_materialize_rev_1.0_i32() { + call void asm sideeffect "; use $0", "s"(i32 508) + ret void +} |