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| author | Carl Ritson <carl.ritson@amd.com> | 2019-03-05 12:21:44 +0000 |
|---|---|---|
| committer | Carl Ritson <carl.ritson@amd.com> | 2019-03-05 12:21:44 +0000 |
| commit | 9e3f7d8ad00caccf20e0daf52657be4cb6270706 (patch) | |
| tree | 421f22d2674b2b2af33e5c1391ad1919be3dc405 /llvm/test/CodeGen/AMDGPU/atomic_optimizations_struct_buffer.ll | |
| parent | 4511f3fa86de9579ded704b66a52492bc7ca08de (diff) | |
| download | bcm5719-llvm-9e3f7d8ad00caccf20e0daf52657be4cb6270706.tar.gz bcm5719-llvm-9e3f7d8ad00caccf20e0daf52657be4cb6270706.zip | |
[AMDGPU] Fix DPP operand order in atomic optimizer
Summary:
Ensure order of operands in DPP atomic optimizer final WWM step is appropriate for sub instructions.
Change-Id: I631d050e1c00a3b4bc7c11a90437064403c4cf30
Reviewers: sheredom, tpr
Reviewed By: sheredom
Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, t-tye, jfb, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D58900
llvm-svn: 355394
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/atomic_optimizations_struct_buffer.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/atomic_optimizations_struct_buffer.ll | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_struct_buffer.ll b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_struct_buffer.ll index eb3f0ab17ac..47fed39cdec 100644 --- a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_struct_buffer.ll +++ b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_struct_buffer.ll @@ -117,7 +117,9 @@ entry: ; GFX7LESS-NOT: v_mbcnt_hi_u32_b32 ; GFX7LESS-NOT: s_bcnt1_i32_b64 ; GFX7LESS: buffer_atomic_sub v{{[0-9]+}} -; GFX8MORE: v_readlane_b32 s[[scalar_value:[0-9]+]], v{{[0-9]+}}, 63 +; GFX8MORE: v_mov_b32_dpp v{{[0-9]+}}, v[[sub_value:[0-9]+]] wave_shr:1 row_mask:0xf bank_mask:0xf +; GFX8MORE: v_sub_u32_e32 v[[sub_value]],{{( vcc,)?}} v[[sub_value]], v{{[0-9]+}} +; GFX8MORE: v_readlane_b32 s[[scalar_value:[0-9]+]], v[[sub_value]], 63 ; GFX8MORE: v_mov_b32{{(_e[0-9]+)?}} v[[value:[0-9]+]], s[[scalar_value]] ; GFX8MORE: buffer_atomic_sub v[[value]] define amdgpu_kernel void @sub_i32_varying_vdata(i32 addrspace(1)* %out, <4 x i32> %inout) { |
