[AMDGPU] Pattern for v_xor3_b32

This also allows three op patterns to use increased constant bus
limit of GFX10.

Differential Revision: https://reviews.llvm.org/D61763

llvm-svn: 360395

1 files changed, 31 insertions, 0 deletions

diff --git a/llvm/test/CodeGen/AMDGPU/and_or.ll b/llvm/test/CodeGen/AMDGPU/and_or.ll
index c8ff582976c..9f4b049ba4d 100644
--- a/llvm/test/CodeGen/AMDGPU/and_or.ll
+++ b/llvm/test/CodeGen/AMDGPU/and_or.ll
@@ -1,6 +1,7 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ;RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=fiji -verify-machineinstrs | FileCheck -check-prefix=VI %s
 ;RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx900 -verify-machineinstrs | FileCheck -check-prefix=GFX9 %s
+;RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 -verify-machineinstrs | FileCheck -check-prefix=GFX10 %s
 
 ; ===================================================================================
 ; V_AND_OR_B32
@@ -17,6 +18,11 @@ define amdgpu_ps float @and_or(i32 %a, i32 %b, i32 %c) {
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_and_or_b32 v0, v0, v1, v2
 ; GFX9-NEXT:    ; return to shader part epilog
+;
+; GFX10-LABEL: and_or:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    v_and_or_b32 v0, v0, v1, v2
+; GFX10-NEXT:    ; return to shader part epilog
   %x = and i32 %a, %b
   %result = or i32 %x, %c
   %bc = bitcast i32 %result to float
@@ -36,6 +42,11 @@ define amdgpu_ps float @and_or_vgpr_b(i32 inreg %a, i32 %b, i32 inreg %c) {
 ; GFX9-NEXT:    v_and_b32_e32 v0, s2, v0
 ; GFX9-NEXT:    v_or_b32_e32 v0, s3, v0
 ; GFX9-NEXT:    ; return to shader part epilog
+;
+; GFX10-LABEL: and_or_vgpr_b:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    v_and_or_b32 v0, s2, v0, s3
+; GFX10-NEXT:    ; return to shader part epilog
   %x = and i32 %a, %b
   %result = or i32 %x, %c
   %bc = bitcast i32 %result to float
@@ -53,6 +64,11 @@ define amdgpu_ps float @and_or_vgpr_ab(i32 %a, i32 %b, i32 inreg %c) {
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_and_or_b32 v0, v0, v1, s2
 ; GFX9-NEXT:    ; return to shader part epilog
+;
+; GFX10-LABEL: and_or_vgpr_ab:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    v_and_or_b32 v0, v0, v1, s2
+; GFX10-NEXT:    ; return to shader part epilog
   %x = and i32 %a, %b
   %result = or i32 %x, %c
   %bc = bitcast i32 %result to float
@@ -70,6 +86,11 @@ define amdgpu_ps float @and_or_vgpr_const(i32 %a, i32 %b) {
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_and_or_b32 v0, v0, 4, v1
 ; GFX9-NEXT:    ; return to shader part epilog
+;
+; GFX10-LABEL: and_or_vgpr_const:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    v_and_or_b32 v0, v0, 4, v1
+; GFX10-NEXT:    ; return to shader part epilog
   %x = and i32 4, %a
   %result = or i32 %x, %b
   %bc = bitcast i32 %result to float
@@ -88,6 +109,11 @@ define amdgpu_ps float @and_or_vgpr_const_inline_const(i32 %a) {
 ; GFX9-NEXT:    v_mov_b32_e32 v1, 0x808
 ; GFX9-NEXT:    v_and_or_b32 v0, v0, 20, v1
 ; GFX9-NEXT:    ; return to shader part epilog
+;
+; GFX10-LABEL: and_or_vgpr_const_inline_const:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    v_and_or_b32 v0, v0, 20, 0x808
+; GFX10-NEXT:    ; return to shader part epilog
   %x = and i32 20, %a
   %result = or i32 %x, 2056
   %bc = bitcast i32 %result to float
@@ -105,6 +131,11 @@ define amdgpu_ps float @and_or_vgpr_inline_const_x2(i32 %a) {
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_and_or_b32 v0, v0, 4, 1
 ; GFX9-NEXT:    ; return to shader part epilog
+;
+; GFX10-LABEL: and_or_vgpr_inline_const_x2:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    v_and_or_b32 v0, v0, 4, 1
+; GFX10-NEXT:    ; return to shader part epilog
   %x = and i32 4, %a
   %result = or i32 %x, 1
   %bc = bitcast i32 %result to float