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| author | Tom Stellard <thomas.stellard@amd.com> | 2016-03-30 16:35:09 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2016-03-30 16:35:09 +0000 |
| commit | 0bc954e3bc474383f87ab9e55ab1aa5ae996f9c0 (patch) | |
| tree | d428795eaee9170ce8fc563a9634e2568806147e /llvm/test/CodeGen/AMDGPU/and.ll | |
| parent | f76123386a7867ff5fa63a55841668ac098e201e (diff) | |
| download | bcm5719-llvm-0bc954e3bc474383f87ab9e55ab1aa5ae996f9c0.tar.gz bcm5719-llvm-0bc954e3bc474383f87ab9e55ab1aa5ae996f9c0.zip | |
AMDGPU/SI: Enable lanemask tracking in misched
Summary:
This results in higher register usage, but should make it easier for
the compiler to hide latency.
This pass is a prerequisite for some more scheduler improvements, and I
think the increase register usage with this patch is acceptable, because
when combined with the scheduler improvements, the total register usage
will decrease.
shader-db stats:
2382 shaders in 478 tests
Totals:
SGPRS: 48672 -> 49088 (0.85 %)
VGPRS: 34148 -> 34847 (2.05 %)
Code Size: 1285816 -> 1289128 (0.26 %) bytes
LDS: 28 -> 28 (0.00 %) blocks
Scratch: 492544 -> 573440 (16.42 %) bytes per wave
Max Waves: 6856 -> 6846 (-0.15 %)
Wait states: 0 -> 0 (0.00 %)
Depends on D18451
Reviewers: nhaehnle, arsenm
Subscribers: arsenm, llvm-commits
Differential Revision: http://reviews.llvm.org/D18452
llvm-svn: 264876
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/and.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/and.ll | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/and.ll b/llvm/test/CodeGen/AMDGPU/and.ll index 0667f64df33..530b7f2d9d2 100644 --- a/llvm/test/CodeGen/AMDGPU/and.ll +++ b/llvm/test/CodeGen/AMDGPU/and.ll @@ -282,11 +282,11 @@ define void @v_and_multi_use_constant_i64(i64 addrspace(1)* %out, i64 addrspace( ; SI: buffer_load_dwordx2 v{{\[}}[[LO1:[0-9]+]]:[[HI1:[0-9]+]]{{\]}} ; SI-NOT: and ; SI: v_and_b32_e32 v[[RESLO0:[0-9]+]], 63, v[[LO0]] -; SI: v_and_b32_e32 v[[RESLO1:[0-9]+]], 63, v[[LO1]] ; SI-NOT: and -; SI: buffer_store_dwordx2 +; SI: buffer_store_dwordx2 v{{\[}}[[RESLO0]] +; SI: v_and_b32_e32 v[[RESLO1:[0-9]+]], 63, v[[LO1]] ; SI-NOT: and -; SI: buffer_store_dwordx2 +; SI: buffer_store_dwordx2 v{{\[}}[[RESLO1]] define void @v_and_multi_use_inline_imm_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr) { %a = load volatile i64, i64 addrspace(1)* %aptr %b = load volatile i64, i64 addrspace(1)* %aptr |
