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authorYaxun Liu <Yaxun.Liu@amd.com>2018-02-02 16:07:16 +0000
committerYaxun Liu <Yaxun.Liu@amd.com>2018-02-02 16:07:16 +0000
commit2a22c5deff3830d50fbc3f877ab30af9f42792f9 (patch)
tree25b57e509727b39c0a06715cccf5dbab3e1ea67e /llvm/test/CodeGen/AMDGPU/amdpal.ll
parenta43e9653bbb388d7fe3d58541bdf13612705cc8f (diff)
downloadbcm5719-llvm-2a22c5deff3830d50fbc3f877ab30af9f42792f9.tar.gz
bcm5719-llvm-2a22c5deff3830d50fbc3f877ab30af9f42792f9.zip
[AMDGPU] Switch to the new addr space mapping by default
This requires corresponding clang change. Differential Revision: https://reviews.llvm.org/D40955 llvm-svn: 324101
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/amdpal.ll')
-rw-r--r--llvm/test/CodeGen/AMDGPU/amdpal.ll28
1 files changed, 14 insertions, 14 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/amdpal.ll b/llvm/test/CodeGen/AMDGPU/amdpal.ll
index baa56de919e..3aaa5898ba5 100644
--- a/llvm/test/CodeGen/AMDGPU/amdpal.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdpal.ll
@@ -17,14 +17,14 @@ entry:
; PAL: s_load_dwordx4 s{{\[}}[[SCRATCHDESC:[0-9]+]]:{{[0-9]+]}}, s{{\[}}[[GITPTR]]:
; PAL: buffer_store{{.*}}, s{{\[}}[[SCRATCHDESC]]:
-define amdgpu_kernel void @scratch(<2 x i32> %in, i32 %idx, i32* %out) {
+define amdgpu_kernel void @scratch(<2 x i32> %in, i32 %idx, i32 addrspace(5)* %out) {
entry:
- %v = alloca [2 x i32]
- %vv = bitcast [2 x i32]* %v to <2 x i32>*
- store <2 x i32> %in, <2 x i32>* %vv
- %e = getelementptr [2 x i32], [2 x i32]* %v, i32 0, i32 %idx
- %x = load i32, i32* %e
- store i32 %x, i32* %out
+ %v = alloca [2 x i32], addrspace(5)
+ %vv = bitcast [2 x i32] addrspace(5)* %v to <2 x i32> addrspace(5)*
+ store <2 x i32> %in, <2 x i32> addrspace(5)* %vv
+ %e = getelementptr [2 x i32], [2 x i32] addrspace(5)* %v, i32 0, i32 %idx
+ %x = load i32, i32 addrspace(5)* %e
+ store i32 %x, i32 addrspace(5)* %out
ret void
}
@@ -41,14 +41,14 @@ entry:
; PAL: s_load_dwordx4 s{{\[}}[[SCRATCHDESC:[0-9]+]]:{{[0-9]+]}}, s{{\[}}[[GITPTR]]:
; PAL: buffer_store{{.*}}, s{{\[}}[[SCRATCHDESC]]:
-define amdgpu_kernel void @scratch2(<2 x i32> %in, i32 %idx, i32* %out) #0 {
+define amdgpu_kernel void @scratch2(<2 x i32> %in, i32 %idx, i32 addrspace(5)* %out) #0 {
entry:
- %v = alloca [2 x i32]
- %vv = bitcast [2 x i32]* %v to <2 x i32>*
- store <2 x i32> %in, <2 x i32>* %vv
- %e = getelementptr [2 x i32], [2 x i32]* %v, i32 0, i32 %idx
- %x = load i32, i32* %e
- store i32 %x, i32* %out
+ %v = alloca [2 x i32], addrspace(5)
+ %vv = bitcast [2 x i32] addrspace(5)* %v to <2 x i32> addrspace(5)*
+ store <2 x i32> %in, <2 x i32> addrspace(5)* %vv
+ %e = getelementptr [2 x i32], [2 x i32] addrspace(5)* %v, i32 0, i32 %idx
+ %x = load i32, i32 addrspace(5)* %e
+ store i32 %x, i32 addrspace(5)* %out
ret void
}
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