[AMDGPU] Switch to the new addr space mapping by default

This requires corresponding clang change.

Differential Revision: https://reviews.llvm.org/D40955

llvm-svn: 324101

1 files changed, 51 insertions, 51 deletions

diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-inline.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-inline.ll
index 8af4b3348b1..9d81cd54f83 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-inline.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-inline.ll
@@ -1,5 +1,5 @@
-; RUN: opt -mtriple=amdgcn--amdhsa -O3 -S -amdgpu-function-calls -inline-threshold=1 < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-INL1 %s
-; RUN: opt -mtriple=amdgcn--amdhsa -O3 -S -amdgpu-function-calls < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-INLDEF %s
+; RUN: opt -mtriple=amdgcn--amdhsa -data-layout=A5 -O3 -S -amdgpu-function-calls -inline-threshold=1 < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-INL1 %s
+; RUN: opt -mtriple=amdgcn--amdhsa -data-layout=A5 -O3 -S -amdgpu-function-calls < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-INLDEF %s
 
 define coldcc float @foo(float %x, float %y) {
 entry:
@@ -10,30 +10,30 @@ entry:
   ret float %cond
 }
 
-define coldcc void @foo_private_ptr(float* nocapture %p) {
+define coldcc void @foo_private_ptr(float addrspace(5)* nocapture %p) {
 entry:
-  %tmp1 = load float, float* %p, align 4
+  %tmp1 = load float, float addrspace(5)* %p, align 4
   %cmp = fcmp ogt float %tmp1, 1.000000e+00
   br i1 %cmp, label %if.then, label %if.end
 
 if.then:                                          ; preds = %entry
   %div = fdiv float 1.000000e+00, %tmp1
-  store float %div, float* %p, align 4
+  store float %div, float addrspace(5)* %p, align 4
   br label %if.end
 
 if.end:                                           ; preds = %if.then, %entry
   ret void
 }
 
-define coldcc void @foo_private_ptr2(float* nocapture %p1, float* nocapture %p2) {
+define coldcc void @foo_private_ptr2(float addrspace(5)* nocapture %p1, float addrspace(5)* nocapture %p2) {
 entry:
-  %tmp1 = load float, float* %p1, align 4
+  %tmp1 = load float, float addrspace(5)* %p1, align 4
   %cmp = fcmp ogt float %tmp1, 1.000000e+00
   br i1 %cmp, label %if.then, label %if.end
 
 if.then:                                          ; preds = %entry
   %div = fdiv float 2.000000e+00, %tmp1
-  store float %div, float* %p2, align 4
+  store float %div, float addrspace(5)* %p2, align 4
   br label %if.end
 
 if.end:                                           ; preds = %if.then, %entry
@@ -46,11 +46,11 @@ bb:
   ret float %call
 }
 
-define void @foo_noinline(float* nocapture %p) #0 {
+define void @foo_noinline(float addrspace(5)* nocapture %p) #0 {
 entry:
-  %tmp1 = load float, float* %p, align 4
+  %tmp1 = load float, float addrspace(5)* %p, align 4
   %mul = fmul float %tmp1, 2.000000e+00
-  store float %mul, float* %p, align 4
+  store float %mul, float addrspace(5)* %p, align 4
   ret void
 }
 
@@ -63,7 +63,7 @@ entry:
 ; GCN:        tail call float @_Z3sinf(
 define amdgpu_kernel void @test_inliner(float addrspace(1)* nocapture %a, i32 %n) {
 entry:
-  %pvt_arr = alloca [64 x float], align 4
+  %pvt_arr = alloca [64 x float], align 4, addrspace(5)
   %tid = tail call i32 @llvm.amdgcn.workitem.id.x()
   %arrayidx = getelementptr inbounds float, float addrspace(1)* %a, i32 %tid
   %tmp2 = load float, float addrspace(1)* %arrayidx, align 4
@@ -72,22 +72,22 @@ entry:
   %tmp5 = load float, float addrspace(1)* %arrayidx2, align 4
   %c1 = tail call coldcc float @foo(float %tmp2, float %tmp5)
   %or = or i32 %tid, %n
-  %arrayidx5 = getelementptr inbounds [64 x float], [64 x float]* %pvt_arr, i32 0, i32 %or
-  store float %c1, float* %arrayidx5, align 4
-  %arrayidx7 = getelementptr inbounds [64 x float], [64 x float]* %pvt_arr, i32 0, i32 %or
-  call coldcc void @foo_private_ptr(float* %arrayidx7)
-  %arrayidx8 = getelementptr inbounds [64 x float], [64 x float]* %pvt_arr, i32 0, i32 1
-  %arrayidx9 = getelementptr inbounds [64 x float], [64 x float]* %pvt_arr, i32 0, i32 2
-  call coldcc void @foo_private_ptr2(float* %arrayidx8, float* %arrayidx9)
-  call void @foo_noinline(float* %arrayidx7)
+  %arrayidx5 = getelementptr inbounds [64 x float], [64 x float] addrspace(5)* %pvt_arr, i32 0, i32 %or
+  store float %c1, float addrspace(5)* %arrayidx5, align 4
+  %arrayidx7 = getelementptr inbounds [64 x float], [64 x float] addrspace(5)* %pvt_arr, i32 0, i32 %or
+  call coldcc void @foo_private_ptr(float addrspace(5)* %arrayidx7)
+  %arrayidx8 = getelementptr inbounds [64 x float], [64 x float] addrspace(5)* %pvt_arr, i32 0, i32 1
+  %arrayidx9 = getelementptr inbounds [64 x float], [64 x float] addrspace(5)* %pvt_arr, i32 0, i32 2
+  call coldcc void @foo_private_ptr2(float addrspace(5)* %arrayidx8, float addrspace(5)* %arrayidx9)
+  call void @foo_noinline(float addrspace(5)* %arrayidx7)
   %and = and i32 %tid, %n
-  %arrayidx11 = getelementptr inbounds [64 x float], [64 x float]* %pvt_arr, i32 0, i32 %and
-  %tmp12 = load float, float* %arrayidx11, align 4
+  %arrayidx11 = getelementptr inbounds [64 x float], [64 x float] addrspace(5)* %pvt_arr, i32 0, i32 %and
+  %tmp12 = load float, float addrspace(5)* %arrayidx11, align 4
   %c2 = call coldcc float @sin_wrapper(float %tmp12)
-  store float %c2, float* %arrayidx7, align 4
+  store float %c2, float addrspace(5)* %arrayidx7, align 4
   %xor = xor i32 %tid, %n
-  %arrayidx16 = getelementptr inbounds [64 x float], [64 x float]* %pvt_arr, i32 0, i32 %xor
-  %tmp16 = load float, float* %arrayidx16, align 4
+  %arrayidx16 = getelementptr inbounds [64 x float], [64 x float] addrspace(5)* %pvt_arr, i32 0, i32 %xor
+  %tmp16 = load float, float addrspace(5)* %arrayidx16, align 4
   store float %tmp16, float addrspace(1)* %arrayidx, align 4
   ret void
 }
@@ -96,23 +96,23 @@ entry:
 ; GCN: %div.i{{[0-9]*}} = fdiv float 2.000000e+00, %tmp1.i
 define amdgpu_kernel void @test_inliner_multi_pvt_ptr(float addrspace(1)* nocapture %a, i32 %n, float %v) {
 entry:
-  %pvt_arr1 = alloca [32 x float], align 4
-  %pvt_arr2 = alloca [32 x float], align 4
+  %pvt_arr1 = alloca [32 x float], align 4, addrspace(5)
+  %pvt_arr2 = alloca [32 x float], align 4, addrspace(5)
   %tid = tail call i32 @llvm.amdgcn.workitem.id.x()
   %arrayidx = getelementptr inbounds float, float addrspace(1)* %a, i32 %tid
   %or = or i32 %tid, %n
-  %arrayidx4 = getelementptr inbounds [32 x float], [32 x float]* %pvt_arr1, i32 0, i32 %or
-  %arrayidx5 = getelementptr inbounds [32 x float], [32 x float]* %pvt_arr2, i32 0, i32 %or
-  store float %v, float* %arrayidx4, align 4
-  store float %v, float* %arrayidx5, align 4
-  %arrayidx8 = getelementptr inbounds [32 x float], [32 x float]* %pvt_arr1, i32 0, i32 1
-  %arrayidx9 = getelementptr inbounds [32 x float], [32 x float]* %pvt_arr2, i32 0, i32 2
-  call coldcc void @foo_private_ptr2(float* %arrayidx8, float* %arrayidx9)
+  %arrayidx4 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %pvt_arr1, i32 0, i32 %or
+  %arrayidx5 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %pvt_arr2, i32 0, i32 %or
+  store float %v, float addrspace(5)* %arrayidx4, align 4
+  store float %v, float addrspace(5)* %arrayidx5, align 4
+  %arrayidx8 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %pvt_arr1, i32 0, i32 1
+  %arrayidx9 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %pvt_arr2, i32 0, i32 2
+  call coldcc void @foo_private_ptr2(float addrspace(5)* %arrayidx8, float addrspace(5)* %arrayidx9)
   %xor = xor i32 %tid, %n
-  %arrayidx15 = getelementptr inbounds [32 x float], [32 x float]* %pvt_arr1, i32 0, i32 %xor
-  %arrayidx16 = getelementptr inbounds [32 x float], [32 x float]* %pvt_arr2, i32 0, i32 %xor
-  %tmp15 = load float, float* %arrayidx15, align 4
-  %tmp16 = load float, float* %arrayidx16, align 4
+  %arrayidx15 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %pvt_arr1, i32 0, i32 %xor
+  %arrayidx16 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %pvt_arr2, i32 0, i32 %xor
+  %tmp15 = load float, float addrspace(5)* %arrayidx15, align 4
+  %tmp16 = load float, float addrspace(5)* %arrayidx16, align 4
   %tmp17 = fadd float %tmp15, %tmp16
   store float %tmp17, float addrspace(1)* %arrayidx, align 4
   ret void
@@ -123,23 +123,23 @@ entry:
 ; GCN-INLDEF: %div.i{{[0-9]*}} = fdiv float 2.000000e+00, %tmp1.i
 define amdgpu_kernel void @test_inliner_multi_pvt_ptr_cutoff(float addrspace(1)* nocapture %a, i32 %n, float %v) {
 entry:
-  %pvt_arr1 = alloca [32 x float], align 4
-  %pvt_arr2 = alloca [33 x float], align 4
+  %pvt_arr1 = alloca [32 x float], align 4, addrspace(5)
+  %pvt_arr2 = alloca [33 x float], align 4, addrspace(5)
   %tid = tail call i32 @llvm.amdgcn.workitem.id.x()
   %arrayidx = getelementptr inbounds float, float addrspace(1)* %a, i32 %tid
   %or = or i32 %tid, %n
-  %arrayidx4 = getelementptr inbounds [32 x float], [32 x float]* %pvt_arr1, i32 0, i32 %or
-  %arrayidx5 = getelementptr inbounds [33 x float], [33 x float]* %pvt_arr2, i32 0, i32 %or
-  store float %v, float* %arrayidx4, align 4
-  store float %v, float* %arrayidx5, align 4
-  %arrayidx8 = getelementptr inbounds [32 x float], [32 x float]* %pvt_arr1, i32 0, i32 1
-  %arrayidx9 = getelementptr inbounds [33 x float], [33 x float]* %pvt_arr2, i32 0, i32 2
-  call coldcc void @foo_private_ptr2(float* %arrayidx8, float* %arrayidx9)
+  %arrayidx4 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %pvt_arr1, i32 0, i32 %or
+  %arrayidx5 = getelementptr inbounds [33 x float], [33 x float] addrspace(5)* %pvt_arr2, i32 0, i32 %or
+  store float %v, float addrspace(5)* %arrayidx4, align 4
+  store float %v, float addrspace(5)* %arrayidx5, align 4
+  %arrayidx8 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %pvt_arr1, i32 0, i32 1
+  %arrayidx9 = getelementptr inbounds [33 x float], [33 x float] addrspace(5)* %pvt_arr2, i32 0, i32 2
+  call coldcc void @foo_private_ptr2(float addrspace(5)* %arrayidx8, float addrspace(5)* %arrayidx9)
   %xor = xor i32 %tid, %n
-  %arrayidx15 = getelementptr inbounds [32 x float], [32 x float]* %pvt_arr1, i32 0, i32 %xor
-  %arrayidx16 = getelementptr inbounds [33 x float], [33 x float]* %pvt_arr2, i32 0, i32 %xor
-  %tmp15 = load float, float* %arrayidx15, align 4
-  %tmp16 = load float, float* %arrayidx16, align 4
+  %arrayidx15 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %pvt_arr1, i32 0, i32 %xor
+  %arrayidx16 = getelementptr inbounds [33 x float], [33 x float] addrspace(5)* %pvt_arr2, i32 0, i32 %xor
+  %tmp15 = load float, float addrspace(5)* %arrayidx15, align 4
+  %tmp16 = load float, float addrspace(5)* %arrayidx16, align 4
   %tmp17 = fadd float %tmp15, %tmp16
   store float %tmp17, float addrspace(1)* %arrayidx, align 4
   ret void