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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2015-09-25 20:22:12 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2015-09-25 20:22:12 +0000 |
| commit | 10aa8078566379592f36487fe9aa9e6b489d55cc (patch) | |
| tree | a58c42598e751da19b6bb0e043f37efd92d23ca5 /llvm/test/CodeGen/AMDGPU/address-space.ll | |
| parent | d9f102b464d5074e7aac7eef49c49e606c892d59 (diff) | |
| download | bcm5719-llvm-10aa8078566379592f36487fe9aa9e6b489d55cc.tar.gz bcm5719-llvm-10aa8078566379592f36487fe9aa9e6b489d55cc.zip | |
PeepholeOptimizer: Remove redundant copies
If a virtual register is copied and another copy was already
seen, replace with the previous copy. This only handles the
simplest cases for now.
This pattern shows up from various operand restrictions
AMDGPU has which require inserting copies depending
on the register class of the operands.
llvm-svn: 248611
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/address-space.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/address-space.ll | 6 |
1 files changed, 1 insertions, 5 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/address-space.ll b/llvm/test/CodeGen/AMDGPU/address-space.ll index 4be8c584752..3aa2f653bf9 100644 --- a/llvm/test/CodeGen/AMDGPU/address-space.ll +++ b/llvm/test/CodeGen/AMDGPU/address-space.ll @@ -5,15 +5,11 @@ %struct.foo = type { [3 x float], [3 x float] } -; FIXME: Extra V_MOV from SGPR to VGPR for second read. The address is -; already in a VGPR after the first read. - ; CHECK-LABEL: {{^}}do_as_ptr_calcs: ; CHECK: s_load_dword [[SREG1:s[0-9]+]], -; CHECK: v_mov_b32_e32 [[VREG2:v[0-9]+]], [[SREG1]] ; CHECK: v_mov_b32_e32 [[VREG1:v[0-9]+]], [[SREG1]] ; CHECK-DAG: ds_read_b32 v{{[0-9]+}}, [[VREG1]] offset:12 -; CHECK-DAG: ds_read_b32 v{{[0-9]+}}, [[VREG2]] offset:20 +; CHECK-DAG: ds_read_b32 v{{[0-9]+}}, [[VREG1]] offset:20 define void @do_as_ptr_calcs(%struct.foo addrspace(3)* nocapture %ptr) nounwind { entry: %x = getelementptr inbounds %struct.foo, %struct.foo addrspace(3)* %ptr, i32 0, i32 1, i32 0 |
