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| author | Nirav Dave <niravd@google.com> | 2017-11-27 15:28:15 +0000 |
|---|---|---|
| committer | Nirav Dave <niravd@google.com> | 2017-11-27 15:28:15 +0000 |
| commit | db77e57ea86d941a4262ef60261692f4cb6893e6 (patch) | |
| tree | 5ea93e1652b4f3065657d9618c69315582b377a4 /llvm/test/CodeGen/AArch64/tailcall-implicit-sret.ll | |
| parent | 948a915924ded9364ddf2d55ad69f47b37bc0843 (diff) | |
| download | bcm5719-llvm-db77e57ea86d941a4262ef60261692f4cb6893e6.tar.gz bcm5719-llvm-db77e57ea86d941a4262ef60261692f4cb6893e6.zip | |
[DAG] Do MergeConsecutiveStores again before Instruction Selection
Summary:
Now that store-merge is only generates type-safe stores, do a second
pass just before instruction selection to allow lowered intrinsics to
be merged as well.
Reviewers: jyknight, hfinkel, RKSimon, efriedma, rnk, jmolloy
Subscribers: javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D33675
llvm-svn: 319036
Diffstat (limited to 'llvm/test/CodeGen/AArch64/tailcall-implicit-sret.ll')
| -rw-r--r-- | llvm/test/CodeGen/AArch64/tailcall-implicit-sret.ll | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/llvm/test/CodeGen/AArch64/tailcall-implicit-sret.ll b/llvm/test/CodeGen/AArch64/tailcall-implicit-sret.ll index 10c4ba4c31d..f449a7e0658 100644 --- a/llvm/test/CodeGen/AArch64/tailcall-implicit-sret.ll +++ b/llvm/test/CodeGen/AArch64/tailcall-implicit-sret.ll @@ -11,8 +11,8 @@ declare i1024 @test_sret() #0 ; CHECK: mov x[[CALLERX8NUM:[0-9]+]], x8 ; CHECK: mov x8, sp ; CHECK-NEXT: bl _test_sret -; CHECK-NEXT: ldr [[CALLERSRET1:x[0-9]+]], [sp] -; CHECK: str [[CALLERSRET1:x[0-9]+]], [x[[CALLERX8NUM]]] +; CHECK: ldr [[CALLERSRET1:q[0-9]+]], [sp] +; CHECK: str [[CALLERSRET1:q[0-9]+]], [x[[CALLERX8NUM]]] ; CHECK: ret define i1024 @test_call_sret() #0 { %a = call i1024 @test_sret() @@ -23,8 +23,8 @@ define i1024 @test_call_sret() #0 { ; CHECK: mov x[[CALLERX8NUM:[0-9]+]], x8 ; CHECK: mov x8, sp ; CHECK-NEXT: bl _test_sret -; CHECK-NEXT: ldr [[CALLERSRET1:x[0-9]+]], [sp] -; CHECK: str [[CALLERSRET1:x[0-9]+]], [x[[CALLERX8NUM]]] +; CHECK: ldr [[CALLERSRET1:q[0-9]+]], [sp] +; CHECK: str [[CALLERSRET1:q[0-9]+]], [x[[CALLERX8NUM]]] ; CHECK: ret define i1024 @test_tailcall_sret() #0 { %a = tail call i1024 @test_sret() @@ -35,8 +35,8 @@ define i1024 @test_tailcall_sret() #0 { ; CHECK: mov x[[CALLERX8NUM:[0-9]+]], x8 ; CHECK: mov x8, sp ; CHECK-NEXT: blr x0 -; CHECK-NEXT: ldr [[CALLERSRET1:x[0-9]+]], [sp] -; CHECK: str [[CALLERSRET1:x[0-9]+]], [x[[CALLERX8NUM]]] +; CHECK: ldr [[CALLERSRET1:q[0-9]+]], [sp] +; CHECK: str [[CALLERSRET1:q[0-9]+]], [x[[CALLERX8NUM]]] ; CHECK: ret define i1024 @test_indirect_tailcall_sret(i1024 ()* %f) #0 { %a = tail call i1024 %f() |
