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| author | Nirav Dave <niravd@google.com> | 2017-12-02 04:01:26 +0000 |
|---|---|---|
| committer | Nirav Dave <niravd@google.com> | 2017-12-02 04:01:26 +0000 |
| commit | 839ff79a8d29968d01002b997b94897a00242ff0 (patch) | |
| tree | 5d51ae14b51597b20abc692f47ec4237aaebd15e /llvm/test/CodeGen/AArch64/tailcall-explicit-sret.ll | |
| parent | 8e97cca1494ab994a2c338fe19b80ee8ede45f73 (diff) | |
| download | bcm5719-llvm-839ff79a8d29968d01002b997b94897a00242ff0.tar.gz bcm5719-llvm-839ff79a8d29968d01002b997b94897a00242ff0.zip | |
[DAG][AArch64] Disable post-legalization store
Disable post-legalization store for AArch64 backend which is causing
errors out-of-tree.
llvm-svn: 319607
Diffstat (limited to 'llvm/test/CodeGen/AArch64/tailcall-explicit-sret.ll')
| -rw-r--r-- | llvm/test/CodeGen/AArch64/tailcall-explicit-sret.ll | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/llvm/test/CodeGen/AArch64/tailcall-explicit-sret.ll b/llvm/test/CodeGen/AArch64/tailcall-explicit-sret.ll index b60958b5a25..c1579336189 100644 --- a/llvm/test/CodeGen/AArch64/tailcall-explicit-sret.ll +++ b/llvm/test/CodeGen/AArch64/tailcall-explicit-sret.ll @@ -35,7 +35,7 @@ define void @test_tailcall_explicit_sret_alloca_unused() #0 { } ; CHECK-LABEL: _test_tailcall_explicit_sret_alloca_dummyusers: -; CHECK: ldr [[PTRLOAD1:q[0-9]+]], [x0] +; CHECK: ldr [[PTRLOAD1:x[0-9]+]], [x0] ; CHECK: str [[PTRLOAD1]], [sp] ; CHECK: mov x8, sp ; CHECK-NEXT: bl _test_explicit_sret @@ -64,8 +64,8 @@ define void @test_tailcall_explicit_sret_gep(i1024* %ptr) #0 { ; CHECK: mov x[[CALLERX8NUM:[0-9]+]], x8 ; CHECK: mov x8, sp ; CHECK-NEXT: bl _test_explicit_sret -; CHECK-NEXT: ldr [[CALLERSRET1:q[0-9]+]], [sp] -; CHECK: str [[CALLERSRET1:q[0-9]+]], [x[[CALLERX8NUM]]] +; CHECK-NEXT: ldr [[CALLERSRET1:x[0-9]+]], [sp] +; CHECK: str [[CALLERSRET1:x[0-9]+]], [x[[CALLERX8NUM]]] ; CHECK: ret define i1024 @test_tailcall_explicit_sret_alloca_returned() #0 { %l = alloca i1024, align 8 @@ -79,8 +79,8 @@ define i1024 @test_tailcall_explicit_sret_alloca_returned() #0 { ; CHECK-DAG: mov [[FPTR:x[0-9]+]], x0 ; CHECK: mov x0, sp ; CHECK-NEXT: blr [[FPTR]] -; CHECK: ldr [[CALLERSRET1:q[0-9]+]], [sp] -; CHECK: str [[CALLERSRET1:q[0-9]+]], [x[[CALLERX8NUM]]] +; CHECK-NEXT: ldr [[CALLERSRET1:x[0-9]+]], [sp] +; CHECK: str [[CALLERSRET1:x[0-9]+]], [x[[CALLERX8NUM]]] ; CHECK: ret define void @test_indirect_tailcall_explicit_sret_nosret_arg(i1024* sret %arg, void (i1024*)* %f) #0 { %l = alloca i1024, align 8 @@ -94,8 +94,8 @@ define void @test_indirect_tailcall_explicit_sret_nosret_arg(i1024* sret %arg, v ; CHECK: mov x[[CALLERX8NUM:[0-9]+]], x8 ; CHECK: mov x8, sp ; CHECK-NEXT: blr x0 -; CHECK: ldr [[CALLERSRET1:q[0-9]+]], [sp] -; CHECK: str [[CALLERSRET1:q[0-9]+]], [x[[CALLERX8NUM]]] +; CHECK-NEXT: ldr [[CALLERSRET1:x[0-9]+]], [sp] +; CHECK: str [[CALLERSRET1:x[0-9]+]], [x[[CALLERX8NUM]]] ; CHECK: ret define void @test_indirect_tailcall_explicit_sret_(i1024* sret %arg, i1024 ()* %f) #0 { %ret = tail call i1024 %f() |
